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| 型号： | IDT74ALVCH162260PA8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 编、解码器及复用、解复用 |
| 英文描述： | ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| 封装： | 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 1/8页 |
| 文件大小： | 77K |
| 代理商： | IDT74ALVCH162260PA8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4628/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This multiplexed D-type latch is built using advanced dual metal CMOS
technology. The ALVCH162260 is used in applications in which two
separate data paths must be multiplexed onto, or demultiplexed from, a
singledatapath.Typicalapplicationsincludemultiplexingand/ordemultiplexing
address and data information in microprocessor or bus-interface applica-
tions. This device also is useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output-enable (
OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The OE1B
and
OE2B control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage
latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are
used to control data storage. When the latch-enable input is high, the latch
is transparent. When the latch-enable input goes low, the data present at
the inputs is latched and remains latched until the latch-enable input is
returned high.
The ALVCH162260 has series resistors in the device output structure
of the “B” port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive ±12mA at the designated
threshold levels. The “A” port has a ± 24mA driver.
The ALVCH162260 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
Balanced Output Drivers: ±12mA (A port)
High Output Drivers: ±24mA (B port)
IDT74ALVCH162260
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS AND
BUS-HOLD
LE1B
LEA1B
OE1B
SEL
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATC H
1B-A
LATC H
A-2B
LATC H
2B-A
LATC H
M
U
X
1
0
12
1B1:12
2B1:12
12
30
29
2
28
1
27
55
56
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