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参数资料
| 型号： | IDT74LVC823ASO8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封装： | 1.27 MM PITCH, SOIC-24 |
| 文件页数： | 2/6页 |
| 文件大小： | 116K |
| 代理商： | IDT74LVC823ASO8 |
2
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Description
Max.
Unit
VTERM(2)
Terminal Voltage with Respect to GND
– 0.5 to +6.5
V
VTERM(3)
Terminal Voltage with Respect to GND
– 0.5 to +6.5
V
TSTG
Storage Temperature
– 65 to +150
°C
IOUT
DC Output Current
– 50 to +50
mA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
– 50
mA
ICC
ISS
Continuous Current through
each VCC or GND
±100
mA
8LVC
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.
This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied.
Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output
Capacitance
VOUT = 0V
5.5
8
pF
CI/O
I/O Port
Capacitance
VIN = 0V
6.5
8
pF
8LVC Link
NOTE:
1. As applicable to the device type.
2
3
1
D
VCC
20
19
18
5
Q
4
Q
6
Q
2
Q
1
Q
3
Q
15
8
Q
9
Q
16
9
10
8
D
7
Q
23
22
24
21
17
OE
5
6
D
7
4
D
5
D
4
2
D
3
D
SO24-2
SO24-7
SO24-8
SO24-9
8
9
D
7
D
13
CLKEN
CLK
14
11
12
CLR
GN D
PIN DESCRIPTION
Pin Names
Description
OE
Output-enable Input (Active LOW)
CLK
Clock Input
CLKEN
Clock-enable Input (Active LOW)
CLR
Clear Input (Active LOW)
xD
Data Inputs
xQ
Data Outputs
FUNCTION TABLE (each flip-flop)
(1)
Inputs
Outputs
OE
CLR
CLKEN
CLK
xD
xQ
LL
X
L
LHL
↑
HH
LHL
↑
LL
LH
H
X
Q
0
HX
X
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
Q
0 = Level of Q before the indicated steady-state input conditions
were established.
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