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参数资料
| 型号： | IDT74LVC823ASO8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封装： | 1.27 MM PITCH, SOIC-24 |
| 文件页数： | 4/6页 |
| 文件大小： | 116K |
| 代理商： | IDT74LVC823ASO8 |
4
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC823A
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V±0.2V
VCC = 3.3V±0.3V
Unit
Symbol
Parameter
Test Conditions
Typical
CPD
Power dissipation capacitance per flip-flop outputs enabled
CL = 0pF, f = 10Mhz
—
59
pF
CPD
Power dissipation capacitance per flip-flop outputs disabled
—
46
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.5V±0.2V
VCC = 2.7V
VCC = 3.3V±0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fMAX
—
150
—
150
—
MHz
tPLH
tPHL
Propagation Delay
CLK to xQ
———
8.9
1.4
8
ns
tPHL
Propagation Delay
CLR to xQ
—
8.8
2.5
7.9
ns
tPZH
tPZL
Output Enable Time
OE to xQ
—
8.3
1.6
7.2
ns
tPHZ
tPLZ
Output Disable Time
OE to xQ
———
7.1
1.1
6
ns
tW
Pulse Duration,
CLR LOW
—
3.3
—
3.3
—
ns
Pulse Duration, CLK HIGH or LOW
—
3.3
—
3.3
—
tSU
Setup Time,
CLR inactive before CLK↑
——
1
—
1
—
ns
Setup Time, data before CLK
↑
—
1.3
—
1.3
—
Setup Time,
CLKEN LOW before CLK↑
—
1.8
—
1.8
—
tH
Hold Time, data after CLK
↑
——
2
—
2
—
ns
Hold Time,
CLKEN LOW after CLK↑
—
1.3
—
1.3
—
tSK(0)
Output Skew(2)
———
——
1
ns
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
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