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参数资料
| 型号： | IDT74SSTVN16859PAG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/7页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 13-26BIT SSTL 64-TSSOP |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 2,000 |
| 逻辑类型： | 13 位至 26 位寄存缓冲器，带 SSTL_2 输入和输出 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 位数： | 13，26 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TFSOP （0.240"，6.10mm 宽） |
| 供应商设备封装： | 64-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 74SSTVN16859PAG8 |
5
COMMERCIALTEMPERATURERANGE
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURERANGE
PC1600-PC2700
PC3200
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
CLOCK
Clock Frequency
—
200
—
220
MHz
tw
Pulse Duration, CLK, CLK HIGH or LOW
2.5
—
2.5
—
ns
tACT
DifferentialInputsActiveTime(1)
—22
—
22
ns
tINACT
DifferentialInputsInactiveTime(2)
—22
—
22
ns
tSU
Setup Time, Fast Slew Rate(3,5)
Data Before CLK
↑, CLK↓
0.65
—
0.65
—
ns
Setup Time, Slow Slew Rate(4,5)
0.75
—
0.75
—
ns
tH
Hold Time, Fast Slew Rate(3,5)
Data Before CLK
↑, CLK ↓
0.75
—
0.65
—
ns
Hold Time, Slow Slew Rate(2,5)
0.9
—
0.8
—
ns
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
PC1600-PC2700
PC3200
Symbol
Parameter
Package
Min.
Max.
Min.
Max.
Unit
fMAX
TSSOP, VFQFPN
200
—
220
—
MHz
tPDM
CLK and CLK to Q
TSSOP
1.1
2.4
1.1
2.2
ns
VFQFPN
1.1
2.2
1.1
1.8
tPDMSS
CLK and CLK to Q (simultaneous switching)
TSSOP
—
2.7
—
2.5
ns
VFQFPN
—
2.5
—
((TBD))
tPHL
RESET to Q
TSSOP, VFQFPN
—
5
—
5
ns
NOTES:
1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.
3. For data signal input slew rate is
≥1V/ns.
4. For data signal input slew rate is
≥0.5V/ns and <1V/ns.
5. CLK, CLK signal input slew rates are
≥1V/ns.
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