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参数资料
| 型号： | IDT82V2044EPFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/73页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1 QUAD SHORT 128-TQFP |
| 标准包装： | 15 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 82V2044EPFG |
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12
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
THZ
Input
4
THZ: Transmit Driver Enable
This pin enables or disables all transmitter drivers on a global basis. A low level on this pin enables the drivers while a high level
turns all drivers into high impedance state. Note that functionality of internal circuits is not affected by signal on this pin.
REF
Input
43
REF: Reference Resistor
An external resistor (3 K
, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
SCLKE
Input
5
SCLKE: Serial Clock Edge Select
Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected as shown below:
JTAG Signals
TRST
Input
Pullup
123
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic
operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
TMS
Input
Pullup
124
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edges of TCK. TMS has an internal pull-up
resistor.
TCK
Input
127
TCK: JTAG Test Clock
This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising edges of TCK while the
data on TDO is clocked out of the device on the falling edges of TCK. When TCK is idle at a low level, all stored-state devices
contained in the test logic will retain their state indefinitely.
TDO
Output
Tri-state
126
TDO: JTAG Test Data Output
This is a tri-state output signal and used for reading all the serial configuration and test data from the test logic. The data on TDO
is clocked out of the device on the falling edges of TCK.
TDI
Input
Pullup
125
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pullup resistor. The data on TDI is clocked
into the device on the rising edges of TCK.
Power Supplies and Grounds
VDDIO
-
13, 22
68, 81
99
3.3V I/O Power Supply
GNDIO
-
12, 23
69, 83
98
I/O Ground
VDDT1
VDDT2
VDDT3
VDDT4
-
101, 102
111, 112
45, 46
55, 56
3.3V Power Supply for Transmitter Driver
GNDT1
GNDT2
GNDT3
GNDT4
-
105, 106
115, 116
49, 50
59, 60
Analog Ground for Transmitter Driver
VDDA
-
44, 121 3.3V Analog Core Power Supply
GNDA
-
41, 122 Core Analog Ground
VDDD
-
9, 85
3.3V Digital Core Power Supply
GNDD
-
11, 84 Core Digital Ground
VDDR1
VDDR2
VDDR3
VDDR4
-
110
120
54
64
3.3V Power Supply for Receiver
Table-1 Pin Description (Continued)
Name
Type
TQFP128
Description
SCLKE
SCLK
Low
Rising edge is active edge
High
Falling edge is active edge
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