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参数资料
型号： IDT82V2616BB
厂商： IDT, Integrated Device Technology Inc
文件页数： 18/99页
文件大小： 0K
描述： IC INVERSE MUX 16CH ATM 272-PBGA
标准包装： 1
应用： 无线
接口： Utopia
电源电压： 2.97 V ~ 3.63 V
封装/外壳： 260-BGA
供应商设备封装： 260-PBGA（19x19）
包装： 托盘
安装类型： 表面贴装
其它名称： 82V2616BB
INTERFACE
25
December 4, 2006
IDT82V2616
Inverse Multiplexing for ATM
3.3
EXTERNAL MICROPROCESSOR INTERFACE
The IDT82V2616 uses an embedded controller and a downloaded
software (IMAOS16 or IMAOS16_Slave1) to communicate with the
external microprocessor. The external microprocessor sends commands
to configure the device and read feedbacks. The downloaded software
interprets these commands and the embedded controller executes
these commands. This relieves programmers from accessing vast regis-
ters. Just by accessing a few registers, programmers can use a set of
well-defined commands to communicate with IDT82V2616.
3.3.1
EXTERNAL MICROPROCESSOR INTERFACE SELECTION
The IDT82V2616 supports both non-multiplexed Intel and non-multi-
plexed Motorola microprocessor interfaces. For Intel microprocessor
interface, the MPM pin should be connected to VDD; for Motorola micro-
processor interface, the MPM pin should be connected to ground.
3.3.2
COMMAND FIFOS
The embedded controller uses two FIFOs to communicate with the
external microprocessor. One is Input FIFO, which is used to receive
commands and data from the external microprocessor; the other is
Output FIFO, which is used to send data to the external microprocessor.
The lengths of these two FIFOs are both 16 bytes. These two FIFOs can
only be accessed through registers.
3.3.3
REGISTERS
The IDT82V2616 provides 9 registers for the external micropro-
cessor to load software to the device, send commands and read feed-
backs.
3.3.4
REGISTER MAP
1. IMAOS16 is used when the device is in normal communication while
IMAOS16_Slave is used when the device operates in Slave Mode. Refer to8.1
Group Auto Detect.
Table-4 Register Map
Address
(Hex)
Register
R/W
Map
b7
b6
b5
b4
b3
b2
b1
b0
00
INPUT_FIFO_LENGTH_REG R/W
-
Input_Message_Length[4:0]
01
OUTPUT_FIFO_LENGTH_R
EG
R
-
Output_Message_Length[4:0]
02
OUTPUT_FIFO_DATA_REG
R
Output_Data[7:0]
03
INPUT_FIFO_DATA_REG
R/W
Input_Data[7:0]
04
FIFO_INT_ENABLE_REG
R/W
-----
Input_FIFO_
empty_int_en
Input_FIFO_ov
erflow_int_en
Output_FIFO_msg
_available_int_en
05
FIFO_STATE_REG
R
HW_version
Input_FIFO_
empty_state
Input_FIFO_ov
erflow_state
Output_FIFO_msg
_available_state
06
FIFO_INT_RESET_REG
W
-----
-
Input_FIFO_ov
erflow&empty_i
nt_rst
Output_FIFO_msg
_available_int_rst
07
OUTPUT_FIFO_INTERNAL_
STATE_REG
R
-
Output_remain_msg_length[4:0]
08
INPUT_FIFO_INTERNAL_ST
ATE_REG
R
-
Input_remain_msg_length[4:0]
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