参数资料
型号: IDT82V2616BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/99页
文件大小: 0K
描述: IC INVERSE MUX 16CH ATM 272-PBGA
标准包装: 1
应用: 无线
接口: Utopia
电源电压: 2.97 V ~ 3.63 V
封装/外壳: 260-BGA
供应商设备封装: 260-PBGA(19x19)
包装: 托盘
安装类型: 表面贴装
其它名称: 82V2616BB
PIN DESCRIPTION
13
December 4, 2006
IDT82V2616
Inverse Multiplexing for ATM
RxAddr4
RxAddr3
RxAddr2
RxAddr1
RxAddr0
C18
D16
D17
D18
E15
I
RxAddr[4:0]: Utopia Receive Address
Utopia receive port address driven from the ATM layer to poll and select an appropriate port.
The RxAddr[4:0] input bus are sampled on the rising edge of RxClk.
RxData7
RxData6
RxData5
RxData4
RxData3
RxData2
RxData1
RxData0
B16
A16
C15
B15
A15
D14
C14
B14
High-Z
O
RxData[7:0]: Utopia Receive Data
Utopia 8-bit data bus driven from the IDT82V2616 to the ATM layer.
The RxData[7:0] output bus are updated on the rising edge of RxClk.
RxClav
C17
High-Z
O
RxClav: Utopia Receive Cell Available
Utopia cell available signal. A polled port drives RxClav only during each cycle following one with its
address on the RxAddr lines. The polled port asserts RxClav high to indicate its corresponding FIFO
has a complete cell available for transfer to the ATM layer, otherwise it deasserts the signal.
The RxClav output is updated on the rising edge of RxClk.
Note: This pin requires a pull-down resistor.
RxSOC
C16
High-Z
O
RxSOC: Utopia Receive Start of Cell
Utopia start of cell pulse. It will be driven high when RxData[7:0] contain the first valid byte of a cell.
The RxSOC input is updated on the rising edge of RxClk.
T1/E1 Line Interface
TSD16
TSD15
TSD14
TSD13
TSD12
TSD11
TSD10
TSD9
TSD8
TSD7
TSD6
TSD5
TSD4
TSD3
TSD2
TSD1
U3
T4
R5
V5
U6
T7
R8
V8
U9
U10
V11
R11
T12
U13
V14
R14
O
TSDn: Transmit Side Data Output
TSDn contains the transmit data for the n-th link.
The TSDn output is updated on the rising edge of TSCKn or TSCCK if common clock is used.
Table-1 Pin Description (Continued)
Name
Pin Number
Input/Output
Description
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