参数资料
型号: IDT82V2616BB
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/99页
文件大小: 0K
描述: IC INVERSE MUX 16CH ATM 272-PBGA
标准包装: 1
应用: 无线
接口: Utopia
电源电压: 2.97 V ~ 3.63 V
封装/外壳: 260-BGA
供应商设备封装: 260-PBGA(19x19)
包装: 托盘
安装类型: 表面贴装
其它名称: 82V2616BB
PIN DESCRIPTION
17
December 4, 2006
IDT82V2616
Inverse Multiplexing for ATM
SRAM Interface
EMD7
EMD6
EMD5
EMD4
EMD3
EMD2
EMD1
EMD0
B6
A6
D7
C7
B7
A7
D8
C8
I/O
EMD[7:0]: Data Bus
Data Input/Output pins for the external SRAM. Used for data exchange between the IDT82V2616 and
the external SRAM.
EMA19
EMA18
EMA17
EMA16
EMA15
EMA14
EMA13
EMA12
EMA11
EMA10
EMA9
EMA8
EMA7
EMA6
EMA5
EMA4
EMA3
EMA2
EMA1
EMA0
C9
B9
A9
A10
B10
C10
D10
A11
B11
C11
D11
A12
B12
C12
D12
A13
B13
C13
D13
A14
O
EMA[19:0]: Address Bus
Address of the external SRAM. Used to select a data entry in the external SRAM.
EM_WE
B8
O
EM_WE: Write Enable
Write enable signal for the external SRAM. When EM_WE pin and EM_CS pin are both low, data can
be written to the external SRAM.
EM_OE
D9
O
EM_OE: Output Enable
Output enable signal for the external SRAM. When EM_OE pin and EM_CS pin are both low, data can
be read from the external SRAM.
EM_CS
A8
O
EM_CS: Chip Select
Chip enable signal for the external SRAM.
JTAG & Scan Interface
TCK
B4
I
TCK: JTAG Test Clock
This pin is the input clock for JTAG.
TMS
A3
I
TMS: JTAG Test Mode Select
This pin has an internal pull-up resistor.
TDI
A4
I
TDI: JTAG Test Data Input
This pin is used to load instructions and data into the test logic and has an internal pull-up resistor.
TDO
C4
High-Z
TDO: JTAG Test Data Output
This is normally high impedance and is used to read all the serial configuration and test data from the
test logic.
TRST
B3
I
TRST: JTAG Test Port Reset
This pin has an internal pull-up resistor.
Table-1 Pin Description (Continued)
Name
Pin Number
Input/Output
Description
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