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| 型号： | IDT82V3001APV |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | WAN PLL WITH SINGLE REFERENCE INPUT |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO56 |
| 封装： | SSOP-56 |
| 文件页数： | 17/27页 |
| 文件大小： | 345K |
| 代理商： | IDT82V3001APV |
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17
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT INDUSTRIAL TEMPERATURE RANGE
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
In the case of the IDT82V3001A, the output signal phase continuity is
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns/125 μs. This meets AT&T TR62411 maximum
phase slope requirement of 7.6 ns/125 μs and Telcordia GR-1244-
CORE (81 ns/1.326 ms).
4.12
PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many
factors, which include:
i) Initial input to output phase difference
ii) Initial input to output frequency difference
iii) Synchronizer loop filter
iv) Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3001A
loop filter and limiter were optimized to meet AT&T TR62411 jitter
transfer and phase slope requirements. Consequently, phase lock time,
which is not a standards requirement, may be longer than in other
applications. See
Table - 7
for Maximum Phase Lock Time.
The IDT82V3001A provides a fast lock pin (FLOCK), which enables
the DPLL to lock to an incoming reference within approximately 500 ms
when set high.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3001APVG | 功能描述:IC PLL WAN W/SGL REF INP 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| IDT82V3001APVG8 | 功能描述:IC PLL WAN W/SGL REF INP 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3002A | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A-01PVG | 功能描述:IC PLL WAN T1/E1 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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