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| 型号： | IDT82V3288BC |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA208 |
| 封装： | PLASTIC, CABGA-208 |
| 文件页数： | 30/170页 |
| 文件大小： | 1053K |
| 代理商： | IDT82V3288BC |
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IDT82V3288
WAN PLL
Functional Description
30
June 22, 2006
3.8
SELECTED INPUT CLOCK SWITCH
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
Chapter 3.6.1 External Fast Selection (T0 only)
&
Chapter 3.6.2 Forced
Selection
) any time. In this case, whether the input clock is qualified for
DPLL locking does not affect the clock switch. If the T4 selected input
clock is a T0 DPLL output, it can only be switched by setting the
T0_FOR_T4 bit.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity, priority and locking allowance con-
figuration. If the current selected input clock is disqualified, a new quali-
fied input clock may be switched to.
3.8.1
INPUT CLOCK VALIDITY
For all the input clocks, the validity depends on the results of input
clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality Moni-
toring
). When all of the following conditions are satisfied, the input clock
is valid; otherwise, it is invalid.
No LOS (the AMI1_LOS / AMI2_LOS bit is ‘0’);
No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
The validity qualification of the T0 selected input clock is different
from that of the T4 selected input clock. The validity qualification of the
T4 selected input clock is the same as the above. The T0 selected input
clock is valid when all of the above and the following conditions are sat-
isfied; otherwise, it is invalid.
No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
The validities of all the input clocks are indicated by the INn
1
bit (14
≥
n
≥
1). When the input clock validity changes (from ‘valid’ to ‘invalid’ or
from ‘invalid’ to ‘valid’), the INn
2
bit will be set. If the INn
3
bit is ‘1’, an
interrupt will be generated.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED
1
bit will be set. If the T0_MAIN_REF_FAILED
2
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
SELECTED INPUT CLOCK SWITCH
When the device is configured as Automatic input clock selection, T0
input clock switch is different from T4 input clock switch.
For T0 path, Revertive and Non-Revertive switches are supported,
as selected by the REVERTIVE_MODE bit.
For T4 path, only Revertive switch is supported.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
Conditions of the qualified input clocks available for T0 selection are
different from that for T4 selection, as shown in
Table 13
:
The input clock is disqualified if any of the above conditions is not
satisfied.
In summary, the selected input clock can be switched by:
External Fast selection (supported by T0 path only);
Forced selection;
Revertive switch;
Non-Revertive switch (supported by T0 path only);
T4 DPLL locked to T0 DPLL output (supported by T4 path only).
3.8.2.1
Revertive Switch
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
The selected input clock is switched if any of the following is satis-
fied:
the selected input clock is disqualified;
another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the highest priority is selected by revertive
switch. If more than one qualified input clock INn is available and has the
same priority, the input clock with the smallest ‘n’ is selected.
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4
Selection
Conditions of Qualified Input Clocks Available for T0 & T4 Selection
T0
Valid, i.e., the INn
1
bit is ‘1’;
Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
are not ‘0000’;
Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
Valid (all the validity conditions listed in
Chapter 3.8.1 Input Clock Valid-
ity
are satisfied);
Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits
are not ‘0000’;
Locking to the input clock is allowed, i.e., the corresponding INn_VALID
bit is ‘0’.
T4
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