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| 型号： | IDT89HPES16NT2ZBBCG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/29页 |
| 文件大小： | 0K |
| 描述： | IC PCI SW 16LANE 2PORT 484-CABGA |
| 标准包装： | 600 |
| 系列： | PRECISE™ |
| 类型： | PCI Express 开关 - Gen1 |
| 应用： | 服务器，储存，通信，嵌入式，消费品 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-CABGA（23x23） |
| 包装： | 带卷 (TR) |
| 其它名称： | 89HPES16NT2ZBBCG8 |
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January 5, 2009
IDT 89HPES16NT2 Data Sheet
Figure 2 PCIe System Interconnect Architecture Block Diagram
Pin Description
The following tables list the functions of the pins provided on the PES16NT2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PEALREV
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[7:0]
PEARN[7:0]
I
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[7:0]
PEATN[7:0]
O
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PECLREV
I
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[7:0]
PECRN[7:0]
I
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[7:0]
PECTN[7:0]
O
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PES16NT2
CPU
PCIe System Interconnect Switch
PES16NT2
CPU
PES16NT2
CPU
Embedded
FC
CPU
Embedded
SATA / SAS
CPU
Embedded
GbE / 10GigE
CPU
相关PDF资料 |
PDF描述 |
|---|---|
| IDT89HPES16NT2ZBBC8 | IC PCI SW 16LANE 2PORT 484-CABGA |
| MIC5310-GFYML TR | IC REG LDO 1.8V/1.5V .15A 8-MLF |
| NCV8537MN250R2G | IC REG LDO 2.5V .7A 10-DFN |
| MIC5320-PKYML TR | IC REG LDO 3V/2.6V .15A 6-MLF |
| IDT89HPES8NT2ZBBCG8 | IC PCI SW 8LANE 2PORT 324-CABGA |
相关代理商/技术参数 |
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|---|---|
| IDT89HPES16T16ZABL | 功能描述:IC PCI SW 16LANE 16PORT 1156BGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89HPES16T4AG2ALGI | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE SW 16LANE 4PORT 324BGA |
| IDT89HPES16T4AG2ALGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE SW 16LANE 4PORT 324BGA |
| IDT89HPES16T4AG2ZBAL | 功能描述:IC PCI SW 16LANDE 4PORT 324FCBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89HPES16T4AG2ZBAL8 | 功能描述:IC PCI SW 16LANDE 4PORT 324FCBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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