参数资料
型号: IDT89HPES16NT2ZBBCG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 26/29页
文件大小: 0K
描述: IC PCI SW 16LANE 2PORT 484-CABGA
标准包装: 600
系列: PRECISE™
类型: PCI Express 开关 - Gen1
应用: 服务器,储存,通信,嵌入式,消费品
安装类型: 表面贴装
封装/外壳: 484-BGA
供应商设备封装: 484-CABGA(23x23)
包装: 带卷 (TR)
其它名称: 89HPES16NT2ZBBCG8
6 of 29
January 5, 2009
IDT 89HPES16NT2 Data Sheet
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 6 Power and Ground Pins
Signal
Type
Name/Description
Table 5 Test Pins (Part 2 of 2)
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