参数资料
型号: IDT9DB801CGLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件页数: 3/20页
文件大小: 277K
代理商: IDT9DB801CGLFT
11
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PD_Mode
PD# drive mode
RW
driven
Hi-Z
0
Bit 6
STOP_Mode
SRC_Stop# drive mode
RW
driven
Hi-Z
0
Bit 5
Reserved
RW
X
Bit 4
Reserved
RW
X
Bit 3
Reserved
RW
X
Bit 2
PLL_BW#
Select PLL BW
RW
High BW
Low BW
1
Bit 1
BYPASS#
BYPASS#/PLL
RW
fan-out
ZDB
1
Bit 0
SRC_DIV#
SRC Divide by 2 Select
RW
x/2
1x
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DIF_7
Output Control
RW
Disable
Enable
1
Bit 6
DIF_6
Output Control
RW
Disable
Enable
1
Bit 5
DIF_5
Output Control
RW
Disable
Enable
1
Bit 4
DIF_4
Output Control
RW
Disable
Enable
1
Bit 3
DIF_3
Output Control
RW
Disable
Enable
1
Bit 2
DIF_2
Output Control
RW
Disable
Enable
1
Bit 1
DIF_1
Output Control
RW
Disable
Enable
1
Bit 0
DIF_0
Output Control
RW
Disable
Enable
1
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DIF_7
Output Control
RW
Free-run Stoppable
0
Bit 6
DIF_6
Output Control
RW
Free-run Stoppable
0
Bit 5
DIF_5
Output Control
RW
Free-run Stoppable
0
Bit 4
DIF_4
Output Control
RW
Free-run Stoppable
0
Bit 3
DIF_3
Output Control
RW
Free-run Stoppable
0
Bit 2
DIF_2
Output Control
RW
Free-run Stoppable
0
Bit 1
DIF_1
Output Control
RW
Free-run Stoppable
0
Bit 0
DIF_0
Output Control
RW
Free-run Stoppable
0
Reserved
12,13
8,9
34,33
30,29
20,21
16,17
8,9
Byte 2
42,41
38,37
30,29
20,21
16,17
12,13
Byte 0
-
Reserved
-
Reserved
Byte 1
42,41
38,37
34,33
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