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参数资料
| 型号： | IDTNW6006AS |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 20/22页 |
| 文件大小： | 0K |
| 描述： | IC CALLER ID DECODER 20-SOIC |
| 标准包装： | 37 |
| 类型： | 来电身份解码器 |
| 应用： | 传真，调制解调器，寻呼机 |
| 电压 - 电源，模拟： | 2.5 V ~ 3.8 V |
| 电压 - 电源，数字： | 2.5 V ~ 3.8 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
| 其它名称： | NW6006AS |
7
INDUSTRIAL TEMPERATURE RANGE
NW6006 ENHANCED TYPE II CALLER ID DECODER
WITH STUTTER DIAL TONE DETECTOR
STUTTER DIAL TONE DETECTION
In some specifications, Stutter Dial Tone is used to indicate voice
mails. The low and high tone frequencies of Stuttered Dial Tone signal
are 350 Hz (tolerant range: 343 Hz to 357 Hz) and 440 Hz (tolerant
range: 431 Hz to 449 Hz).
When the device selects Stutter Dial Tone detection, the bi-
purpose output pin CD/STRDT is STRDT. STRDT goes low when dial
tone signal has been detected and return high after dial tone signal
has been ended (see Fig. 21).
The incoming Stuttered Dial Tone signal goes through anti-alias
filter and then is separated into high band and low band by two
bandpass filters. The tone detection algorithm examines the filter
outputs to validate the arrival of the Stutter Dial Tone signal. An
embeded digital algorithm implements guard-time function. If the dial
tone signal is qualified by the algorithm, the STRDT pin goes active to
indicate a correct detection.
FSK DEMODULATION
The key part among the functions offered by NW6006 is FSK
demodulation. This function is implemented by several stages: first,
the carrier detector provides an indication of the presence of signal at
the bandpass filter output; second, the device’s dual mode serial
interface allows convenient extraction of the 8-bit data words in the
demodulated FSK bit stream.
The FSK characteristics are different in BT, ETSI and Bellcore
specifications. The signal frequencies in BT and ETSI correspond to
ITU-T V.23; the Bellcore frequencies correspond to Bell 202. The
NW6006 is compatible with both formats. It also meets the signal
characteristics by setting the Tip/Ring input OP amp at unity gain in 5V
operation.
ITU-T V.23
Bell 202
Mark Freq. (‘1’)
1300 Hz ± 1.5%
1200 Hz ± 1%
Space Freq. (‘0’)
2100 Hz ± 1.5%
2200 Hz ± 1%
For 3 V operation, the FSK receiver becomes easier to accept
lower level signals than in 5 V operation. The Tip/Ring input OP amp
gain should be reduced to maintain the FSK reject level.
Serial FSK Interface
The three wire DATA, DCLK and DR form the data interface of the
FSK demodulation. The DATA pin is the serial data pin that outputs
data to external devices. The DCLK pin is the data clock which is used
in Mode ‘1’ and is generated by an external device. The DR pin is the
data ready signal used in Mode ‘1’, also an output from the NW6006
to external devices. DR/STD pin is a dual purpose output pin, when
FSK function is selected it is DR.
Two modes are selectable via control of the device’s CB0 pin:
Mode ‘0’ (CB0 is low), where the FSK bit stream is output directly;
Mode ‘1’ (CB0 is high), where the data byte and the stop bit are stored
in a 9 bit buffer.
Mode ‘0’ (CB0 is low)
In this mode, the device demodulates the incoming FSK signal,
and output the data directly to the DATA pin. DCLK and DR pins are
unused. Fig. 19 and Fig. 20 show the timing diagram of Mode ‘0’
operation.
Mode ‘1’ (CB0 is high)
In this mode, the received byte is stored on chip. The
microcontroller supplies read pulses (DCLK) to shift the register
contents serially out of the NW6006, onto the DATA pin. The NW6006
asserts DR to denote the word boundary and indicate to the
microprocessor that a new word has become available. Internal to the
device, the demodulated data bits are sampled and stored. Midway
through the stop bit, the 8 data bits and the stop bit are parallel loaded
into an 9-bit shift register and DR goes low. The contents of register
are shifted out to DATA pin on DCLK’s rising edge with LSB (Least
Significant Bit) out first. If DCLK begins while DR is low, DR will return to
high upon the first DCLK rising edge. This feature allows the
associated interrupt to be cleared by the first read pulse. Otherwise,
DR stays low for half a nominal bit time (1/2400 sec) and then returns
to high. After the last bit (Most Significant Bit) has been read,
additional DCLKs are ignored. Fig. 18 shows the timing diagram of
Mode ‘1’ operation.
Reading the stop bit is a method of checking framing errors. If it’s
certain that there is no framing error would occur, the microcontroller
only needs to send 8 DCLK pulses to shift the data byte out. After the
checksum byte has be received, all 9 bits should be read and framing
error checked.
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