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参数资料
| 型号： | IM42-67025V-55 |
| 厂商： | ATMEL CORP |
| 元件分类： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 55 ns, CQCC84 |
| 封装： | LCC-84 |
| 文件页数： | 5/23页 |
| 文件大小： | 257K |
| 代理商： | IM42-67025V-55 |
M 67025
MATRA MHS
Rev. D (29/09/95)
13
Test Conditions (8)
AC Test Conditions
Input Pulse Levels
: GND to 3.0 V
Input Rise/Fall Times
: 5 ns
Input Timing Reference Levels
: 1.5 V
Output Reference Levels
: 1.5 V
Output Load
: see figures 2, 3
Figure 2. Output Load.
Figure 3. Output Load (for tHZ, tLZ, tWZ, and tOW).
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
READ CYCLE
PARAMETER
M
67025–20
M
67025–25
M
67025–30
M
67025–35
M
67025–45
M
67025–55
UNI
Symbol
(4)
Symbol
(5)
PARAMETER
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
UNI
T
TAVAVR tRC
Read cycle time
20
–
25
–
30
–
35
–
45
–
55
–
ns
TAVQV
tAA
Address access time
–
20
–
25
–
30
–
35
–
45
–
55
ns
TELQV
tACS
Chip Select access
time (3)
–
20
–
25
–
30
–
35
–
45
–
55
ns
TBLQV
tABE
Byte enable access
time (3)
–
20
–
25
–
30
–
35
–
45
–
55
ns
TGLQV
tAOE
Output enable access
time
–
11
–
13
–
15
–
20
–
25
–
30
ns
TAVQX
tOH
Output hold from
address change
3
–
3
–
3
–
3
–
3
–
3
–
ns
TELQZ
tLZ
Output low Z time (1,
2)
3
–
3
–
3
–
3
–
5
–
5
–
ns
TEHQZ
tHZ
Output high Z time (1,
2)
–
15
–
15
–
15
–
15
–
20
–
25
ns
TPU
tPU
Chip Select to power
up time (2)
0
–
0
–
0
–
0
–
0
–
0
–
ns
TPD
tPD
Chip disable to power
down time (2)
–
50
–
50
–
50
–
50
–
50
–
50
ns
TSOP
tSOP
SEM flag update pulse
(OE or SEM)
12
–
12
–
15
–
15
–
15
–
15
–
ns
Notes :
1. Transition is measured
± 500 mV from low or high impedance voltage with load (figures 2 and 3).
2. This parameters is guaranteed but not tested.
3. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to table 1.
4. STD symbol.
5. ALT symbol.
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