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参数资料
| 型号： | IMISC643AYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 5/12页 |
| 文件大小： | 138K |
| 代理商： | IMISC643AYB |
SC643
I
2C Clock Generator for 3 DIMM, Pentium
II Designs
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.6
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 12
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz).
Xin
may also serve as input for an externally generated
reference signal.
REF0 - Buffered output of the crystal.
REF1 / CS# - This pin is bidirectional. If pin 25, MODE
= 1 (default), then this pin is a REF1 buffered output of
the crystal. If pin 25, MODE = 0 then this pin is CS#
and
is
used
in
power
management
mode
for
synchronously stopping the all CPU clocks (see page
4).
CPU (0:3) - Low skew (<250 pS) clock outputs for host
frequencies such as CPU, Chipset, Cache. Vddq2 is the
supply voltage for these outputs.
SDRAM(0:11) - Synchronous DRAM DIMs clocks, they
have the same frequency as CPU clocks.
PCI (2:4) - Low skew (<250pS) PCI clock outputs.
PCI1 / FTS, PCI0 / S2, PCI_F / S1 - Low skew
(<250pS)
PCI
clock
outputs.
These
pins
are
bidirectional. During power-up, These pins are inputs
(FTS, S2 and S1) and are used for HARD selecting the
output frequency of CPU, SDRAM and PCI clocks, see
Frequency table page1 and page 11, fig.3. When the
power reaches the VDD rail (See Fig.1, page3), the
selected data is latched internally to the IC and these
pins become PCI1, PCI0 and PCI_F clock outputs.
PCI5 / PS# - PCI clock output.
This pin is a
bidirectional. If pin 25, MODE = 1 (default), then this
pin is a PCI5 clock output. If pin 25, MODE = 0 then
this pin is PS# and is used in power management
mode for synchronously stopping the all PCI clocks (see
page 4).
IOAPIC - This pin is a high drive buffered output of the
crystal. This pin is powered by VDDq2.
48 MHz / S0 - This is a bidirectional pin. During power-
up, This pin is in input mode and is used for selecting
the output frequency of CPU and SDRAM clocks, see
Frequency table page1 and page 11, fig.3 for jumper
application; this pin has an internal pull-up. When the
power reaches the VDD rail (See Fig.1, page3), the
selected data is latched internally to the IC and this pin
becomes a 48 Mhz output for USB clock.
24 MHz / MODE - This is a bidirectional pin. During
power-up, This pin is an input and is used for enabling
(0) or disabling (1, default) the power management pins
15 and 46. see page 4 and page 11, fig.3 for jumper
application; this pin has an internal pull-up. When power
reaches the VDD rail (See Fig.1, page 3), the selected
data is latched internally to the IC and this pin becomes
a 24 Mhz output for SIO clock.
SDATA - serial data of I
2C 2-wire control interface. Has
internal pull-up resistor.
SDCLK - serial clock of I
2C 2-wire control interface.
Has internal pull-up resistor.
Vss - Circuit Ground.
Vdd - Power supply for analog circuit and core logic.
Vddq3 - Power supply pins for 3.3V IO pins.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
A bypass capacitor (0.1
F) should be placed as
close as possible to each Vdd, Vddq2, and Vddq3
pin. If these bypass capacitors are not close to the
pins their high frequency filtering characteristic will
be cancelled by the lead inductances of the traces.
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