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参数资料
| 型号： | IMISC643AYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 7/12页 |
| 文件大小： | 138K |
| 代理商： | IMISC643AYB |
SC643
I
2C Clock Generator for 3 DIMM, Pentium
II Designs
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.6
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 4 of 12
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
Fig. 2
2-WIRE I
2C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The IMISC643 cannot be read back.
Sub-addressing is not supported, thus all preceeding bytes must be sent in order to change one of the
control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable
when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is
high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is
high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the
LSB. Data is transferred MSB first.
The IMISC643 will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge
(low) signal on the SDATA wire following reception of each byte.
The IMISC643 will not respond to any
other control interface conditions. Previously set control registers are retained.
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