
SC643
I
2C Clock Generator for 3 DIMM, Pentium
II Designs
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.6
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 5 of 12
SERIAL CONTROL REGISTERS
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state
at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN#
pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be
acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below desrcibed sequence
(Byte 0, Byte 1, Byte2, ....) will be valid and acknowledged.
Byte 0: Frequency, Function Select Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
*
FTS (for frequency table selection by software via I2C)
61
*
S2
(for frequency table selection by software via I2C)
51
*
S1
(for frequency table selection by software via I2C)
41
*
S0
(for frequency table selection by software via I2C)
3
0
*
enables freq. selection by hardware (set to 0) or software I2C (set to 1)
2
x
n/a
Reserved for future Spectrum Spread function
1
0
*
Bit1 Bit0
1
1 Tri-State
1
0 Reserved for future Spectrum Spread function
0
1 Reserved for future Spectrum Spread function
0
0 Normal
Function Table
Function
Outputs
Description
CPU
PCI
SDRAM
Ref
IOAPIC
Tri-State
Hi-Z
Normal
see table
CPU
14.318