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参数资料
| 型号： | IMISC680CYB |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 1/8页 |
| 文件大小： | 109K |
| 代理商： | IMISC680CYB |
SC680C
I
2C System Clock Buffer
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.2.3
8/12/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 8
PRODUCT FEATURES
18 output buffer for high clock fanout applications
Each output can be internally disabled for EMI
reduction
VDD=3.3 volts for each 2 clock group
Ouput frequency range 10 Mhz to 100 Mhz
< 250ps skew between output clocks.
48-pin SSOP package
Single Clock Enable pin for testability
BLOCK DIAGRAM
CLK[1:2]
CLK[3:4]
VDD1
CLK[5:6]
CLK[7:8]
CLK[9:10]
CLK[17,18]
SDATA
SCLK
CLK[11:12]
CLK[13:14]
CLK[15:16]
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
Control
Logic
OE
VDD9
REFIN
PRODUCT DESCRIPTION
The IMISC680 is a high fanout system clock buffer. Its
primary application is to create the large quantity of
clocks needed to support a wide range of applications
that
requires
those
clock
loads
signal
that
are
referenced to a single existing clock. Loads of up to 30
pF are supported. One of the chief applications of this
component is where long traces are used to transport
clocks from their generating devices to their loads. The
creation of EMI and the degradation of waveform rise
and fall times is greatly reduced by running a single
reference clock trace to this device and then using it to
regenerate the clock that drives shorter traces. Using
these
devices EMI is therefore minimized and board
real estate is saved.
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
VDD1
CLK1
CLK2
VSS1
VDD2
CLK3
CLK4
VDD3
CLK5
CLK6
VDD4
CLK7
VSS2
VSS3
CLK8
VSS4
CLK9
VSS5
VDD
SDATA
SCLOCK
VSS
CLK10
VDD
VSS6
VDD6
CLK13
CLK14
OE
VSS8
CLK16
VDD8
CLK12
VSS7
VDD7
CLK15
VSS9
CLK17
CLK18
VDD9
NC
VDD5
IMISC680
REFIN
CLK11
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