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参数资料
| 型号： | IMISG570CYB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 7/14页 |
| 文件大小： | 176K |
| 代理商： | IMISG570CYB |
SG570
I
2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
3/23/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 14
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
SEL - Standard frequency select input. It has internal
pull-up.
CPUCLK(0:3) - Low skew (<250 pS) clock outputs for
host frequencies such as CPU, Chipset, Cache. Vddq2
is the supply voltage for these outputs.
SDRAM(0:5) - Synchronous DRAM DIMs clocks. They
are powered by Vddq3.
SDRAM6/CPU_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3. If MODE=0, this pin is a CPU_STOP# input
signal, where a low level stops the CPU however, the
SDRAM clocks will stay active. It has an internal pull-
up.
SDRAM7/PCI_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3.
If MODE=0, this pin is a PCI_STOP# input
signal, where a low level stops the PCI clocks. It has an
internal pull-up.
MODE - A low level on this pin causes pins 26, and 27
to be power management inputs PCI_STOP#, and
CPU_STOP# respectly. A high level on this pin causes
pins 26, and 27 to be clock output signals SDRAM7,
and SDRAM6 respectively. It has an internal pull-up
resistor.
PCICLK(0:5) - Low skew (<250pS) clock outputs for
PCI frequencies.
These buffers voltage level is
controlled by Vddq3
PCICLK_F - A PCI clock output that does not stop until
in power down mode. It is synchronous with other PCI
clocks.
REF(0:1) - Buffered outputs of on-chip reference.
IOAPIC0
-
Buffered
output
of
14.3MHZ
for
multiprocessor support. It is powered by Vddq2.
PWR_DWN# - Power down pin.
When this pin is
asserted low, the IC is in shutdown mode where all
circuitry is turned off including VCO, crystal buffer and
PCICLK_F. It has an internal pull-up. The I
2C interface
is disabled with the PWR_DWN# pin is low.
48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ
clock outputs.
SDATA - serial data of I
2C 2-wire control interface.
Has internal pull-up resistor.
SDCLK - serial clock of I
2C 2-wire control interface.
Has internal pull-up resistor.
Vss - Ground pins for the chip.
Vdd - 3.3 Volt power supply pins for analog circuit and
core logic.
Vddq3 - Power supply pins for 3.3V IO pins.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
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