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参数资料
| 型号： | IMISG570CYB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 9/14页 |
| 文件大小： | 176K |
| 代理商： | IMISG570CYB |
SG570
I
2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
3/23/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 4 of 14
2-WIRE I
2C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The IMISG570D cannot be read back.
Sub-addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes.
The 2-wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ
frequency selection and test mode enable.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to
indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of
a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first
byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low)
signal on the SDATA wire following reception of each byte.
The device will not respond to any other control interface
conditions.
The I
2C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are
retained.
SERIAL CONTROL REGISTERS
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state
at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN#
pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be
acknowledged.
Byte 0: Function Select Register
Bit
@Pup
Pin#
Description
70
*
Reserved
60
*
Reserved
50
*
Reserved
40
*
Reserved
3
1
23
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
2
1
22
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
1
0
Bit1 Bit0
1
1 Tri-State
1
0
Spread Spectrum operating mode
0
1 Test Mode
0
Normal operating mode
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