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参数资料
| 型号： | IN74LV574DW |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal D-type flip-flop; positive edge-trigger (3-State) |
| 中文描述： | 八路D型触发器;上升沿触发（3态） |
| 文件页数： | 5/8页 |
| 文件大小： | 194K |
| 代理商： | IN74LV574DW |
IN74LV574
5
INTEGRAL
Test
V
CC
Guaranteed Limit
85
°
C
Symbol
Parameter
conditions
V
-40
°
C to
25
°
C
125
°
C
Unit
min
max
min
max
min
max
t
w
Pulse Width, Clock (high)
V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
120
29
21
17
15
-
-
-
-
-
34
25
20
-
-
-
41
30
24
-
-
-
ns
t
su
Setup Time, Data to Clock V
I
= 0 V or V
1
Figures 1,5
1.2
2.0
2.7
3.0
4.5
40
19
14
11
9
-
-
-
-
-
22
16
13
-
-
-
26
19
15
-
-
-
ns
t
h
Hold Time, Clock to Data
V
I
= 0 V or V
1
Figures 1,5
1.2
2.0
2.7
3.0
5
5
5
5
-
-
-
-
5
5
5
5
-
-
-
-
5
5
5
5
-
-
-
-
ns
f
c
Clock Frequency
V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
2
17
21
27
31
-
-
-
15
19
24
-
-
-
12
16
20
MHz
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 3. Switching Waveforms
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