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参数资料
| 型号： | IP-RSENC |
| 厂商： | Altera |
| 文件页数： | 19/38页 |
| 文件大小： | 0K |
| 描述： | IP REED-SOLOMON ENCODER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Reed-Solomon 编码器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
Simulate the Design
Table 2–1. Generated Files (Part 2 of 2)
Filename
< variation name > _testbench.vhd
< variation name > _vsim_script.tcl
< variation name >_ block_period_stim.txt
< variation name > _encoded_data.txt
< variation name >.html
< variation name >.qip
(1)
2–9
Description
The testbench variation file, which defines the top-level testbench that
runs the simulation. This file instantiates the function variation file and the
testbench from the reed_solomon\lib directory.
Starts the MegaCore function simulation in the ModelSim simulator.
The testbench stimuli includes information such as number of
codewords, number of symbols, and check symbols for each codeword
Contains the encoded test data.
A MegaCore function report file in hypertext markup language format.
A single Quartus II IP file is generated that contains all of the assignments
and other information required to process your MegaCore function
variation in the Quartus II compiler. You are prompted to add this file to
the current Quartus II project when you exit the parameter editor.
Notes to Table 2–1 :
(1) < variation name > is the variation name.
2. After you review the generation report, click Exit to close IP Toolbench. Then click
Yes on the Quartus II IP Files prompt to add the . qip file describing your custom
MegaCore function to the current Quartus II project.
f Refer to the Quartus II Help for more information about the MegaWizard Plug-In
Manager.
You can now integrate your custom variation into your design and simulate and
compile.
Simulate the Design
IP Toolbench-generated Tcl scripts drive the simulation. For the decoder, the testbench
includes a channel and the instantiated decoder. Data is read from an
IP Toolbench-generated file. For the encoder, the testbench reads the same data file
and just compares the encoder output with a data file. In the channel, some errors are
introduced at various locations of the RS codeword. The testbench then receives the
data decoded by the RS decoder and compares it with the originally transmitted data.
You can perform a simulation in a third-party simulation tool from within the
Quartus II software, using NativeLink.
f For more information about NativeLink, refer to the Simulating Altera Designs chapter
in volume 3 of the Quartus II Handbook .
You can use the Tcl script file < variation name > _nativelink.tcl to assign default
NativeLink testbench settings to the Quartus II project.
To set up simulation in the Quartus II software using NativeLink, follow these steps:
1. Create a custom variation but ensure you specify your variation name to match the
Quartus II project name.
November 2013
Altera Corporation
Reed-Solomon Compiler
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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