参数资料
型号: IP-RSENC
厂商: Altera
文件页数: 6/38页
文件大小: 0K
描述: IP REED-SOLOMON ENCODER
标准包装: 1
系列: *
类型: MegaCore
功能: Reed-Solomon 编码器
许可证: 初始许可证
1–2
Chapter 1: About This Compiler
Release Information
DSP Builder ready
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore Plus evaluation
Release Information
Table 1–1 provides information about this release of the Reed-Solomon (RS) Compiler.
Table 1–1. RS Compiler Release Information
Version
Release Date
Ordering Codes
Product IDs
Vendor ID
Item
Description
12.1
November 2012
IP-RSENC (Encoder)
IP-RSDEC (Decoder)
0039 0041 (Encoder)
0080 0041 (Decoder)
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata .
Altera verifies that the current version of the Quartus ? II software compiles the
previous version of each MegaCore ? function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release.
Device Family Support
Altera offers the following device support levels for Altera IP cores:
Preliminary support —Altera verifies the IP core with preliminary timing models
for this device family. The IP core meets all functional requirements, but might still
be undergoing timing analysis for the device family. You can use it in production
designs with caution.
Final support —Altera verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–2 shows the level of support offered by the RS Compiler to each of the Altera
device families.
Table 1–2. Device Family Support (Part 1 of 2)
Device Family
Support
Arria ?
II GX
Final
Reed-Solomon Compiler
User Guide
Arria II GZ
Arria V
Final
Full
November 2013 Altera Corporation
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