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参数资料
| 型号： | IP1001TR |
| 厂商： | International Rectifier |
| 文件页数： | 1/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 20A 256BGA |
| 标准包装： | 750 |
| 系列： | iPOWIR™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.93 V ~ 2 V |
| 输入电压： | 3.3 V ~ 12 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz，300kHz |
| 电流 - 输出： | 20A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA（218 凸块） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | BGA（14x14） |
| 配用： | IRDCIP1001-A-ND - CONV SGL PHA SYNC BUCK 3.3-4.5V |
PD - 94336c
iP1001
Full Function Synchronous Buck Power Block
Integrated Power Semiconductors, Control IC & Passives
Features
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3.3V to 12V input voltage 1
20A maximum load capability, with no derating up to T PCB = 90°C
5 bit DAC settable, 0.925V to 2V output voltage range 2
Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3
200kHz or 300kHz nominal switching frequency
Optimized for very low power losses
Over & undervoltage protection
Adjustable lossless current limit
Internal features minimize layout sensitivity *
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Very small outline 14mm x 14mm x 3mm
iP1001 Power Block
Description
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
iP1001 Internal Block Diagram
V IN
D0
5 Bit
DAC D3
D1
D2
D4
ENABLE
PGOOD
ILIM
FREQ
V DD
PWM
& Driver
V SW
SGND
GNDS
V FS
V F PGND
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
www.irf.com
05/20/03
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