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参数资料
| 型号： | IP1001TR |
| 厂商： | International Rectifier |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 20A 256BGA |
| 标准包装： | 750 |
| 系列： | iPOWIR™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.93 V ~ 2 V |
| 输入电压： | 3.3 V ~ 12 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz，300kHz |
| 电流 - 输出： | 20A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA（218 凸块） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | BGA（14x14） |
| 配用： | IRDCIP1001-A-ND - CONV SGL PHA SYNC BUCK 3.3-4.5V |
iP1001
Application Issues
Setting V OUT above 2V
In certain applications where the output voltage is
required to be set higher than the maximum DAC
code setting of 2V, it is possible to use an external
resistive voltage divider which, for accuracy, needs
to have 1% or better tolerance. The switching
frequency should be set at 200kHz by connecting
the FREQ pin to V DD . Also, the output voltage should
never be set higher than 3.3V with a V IN minimum of
5V, or 2.5V with a V IN minimum of 3.3V. The DAC
code should be set to 2V and the following equation
used to select the resistors:
V OUT = V F
x
(1 + R3/R4)
See the reference design for reference designators.
Note that the impedance at V F is 180K ? ±35%. It is
recommended that R3 be calculated assuming a
value of 1k ? for R4. Connect V FS to V F and GNDS to
PGND.
Duty Cycle D = V OUT / V IN >50%
For duty cycles >50% the switching frequency should
be set at 200kHz. 300kHz switching frequency can
be selected if the output is less than 2V and the duty
cycle is <50%.
For duty cycles >50%, add external compensation
ramp from the Vsw terminal of the iP1001 device as
shown in the reference design through R9 resistor
and C21 capacitor (Fig 10a.). For optimum perfor-
mance maintain a RC time constant of approximately
5 μ s.
12
www.irf.com
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