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参数资料
| 型号： | IP1001TR |
| 厂商： | International Rectifier |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 20A 256BGA |
| 标准包装： | 750 |
| 系列： | iPOWIR™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.93 V ~ 2 V |
| 输入电压： | 3.3 V ~ 12 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz，300kHz |
| 电流 - 输出： | 20A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA（218 凸块） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | BGA（14x14） |
| 配用： | IRDCIP1001-A-ND - CONV SGL PHA SYNC BUCK 3.3-4.5V |
iP1001
iP1001 Reference Design
The schematics in Fig.10a & 10b and complete Bill
of Materials in Table 4 are provided as a reference
design to enable a preliminary evaluation of iP1001.
They represent a simple method of applying the
iP1001 solution in a synchronous buck topology.
Fig. 10a shows the implementation for <5V IN
nominal applications, and Fig. 10b shows the
implementation for 5V IN - 12V IN nominal
applications.
The connection pins are provided through the solder
balls on the bottom layer of the package. A total
power supply solution is presented with the addition
of inductor L1 and the output capacitors C11-C14.
Input capacitors C1-C10 are for bypassing in the
5V IN - 12V IN application, but only C1-C3 are required
for <5V IN applications (refer to the BOM for values).
Switches 1-5 of SW1 are used to program the output
voltage. Refer to the VID table provided in this
datasheet for the code that corresponds to the
desired output voltage. Resistors R2 & R4 need to
be removed for operation at standard VID levels
(0.925V - 2.0V, leave R3 = 0 ? ). Switch 8 of SW1
enables the output when floating (internally pulled
high). The 5V V DD power terminal and input power
terminals are provided as separate inputs. They
can be connected together if the application
requires only 5V nominal input voltage.
The reference design also offers a higher output
voltage option for greater than 2.0V, up to 3.3V. For
output voltages above 2V, the DAC setting must be
set to 2V, and then select resistors R3 & R4 per
Equation 1 on page 10 for the desired output volt-
age. Remove R5 and connect V F to V FS through R2,
where R2= 0 ?. In this case, GNDS should be refer-
enced to PGND. Tighter regulation can be achieved
by using resistors with less than 1% tolerance. For
Vin < 5V and Vout > 2V, the frequency select pin
(FREQ) must be set to 200kHz (connected to V DD ).
For applications with V IN < 5V and where there is no
auxiliary 5V available, connections JP2 and JP3
must be provided in order to enable the boost cir-
cuit. This will provide 5V V DD necessary for the
iP1001 internal logic to function. The boost circuit
will convert 3.3V input voltage to 5V, to power the
V DD , and will provide enough power to supply the
internal logic for up to five iP1001 power blocks.
14
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