参数资料
型号: IP1201PBF
厂商: International Rectifier
文件页数: 13/29页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 30A 198BGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 10
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 3.3 V
输入电压: 3.14 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 400kHz
电流 - 输出: 30A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 198-BGA(159 凸块)
包装: 散装
供应商设备封装: BGA(15.5x9.25)
配用: IRDCIP1201-A-ND - BUCK CONV REF DESIGN KIT IP1201
iP1201PbF
iP1201PbF User?s Design Guidelines
iP1201
The iP1201PbF can be configured as a dual channel
15A or parallel single 30A power block consisting of
optimized power semiconductors, PWM control and
its associated passive components. It is based on a
synchronous buck topology and offers an optimized
solution where space, efficiency and noise caused by
parasitics are of concern. The phase shifted, two out-
put power block operates with fixed frequency voltage
mode control and can be configured to operate as a
dual output or paralleled single output with current shar-
ing. The iP1201PbF components are integrated in a
ball grid array (BGA) package.
SS1/SS2
10
Iss
iP1201PbF
Css
V IN
The input operating voltage range of the iP1201PbF is
3.14V to 5.5V. Both channels of the power block have a
common input.
For applications where the input bus voltage is less
than 3.5V, A and B pins should be shorted. For input
voltages greater than 3.5V, A and B pins should be
disconnected and floating. Voltages at A and B pins
are internally generated, no external voltage source
should be connected to either one of these pins. A
Power-On-Reset is performed when V IN falls below
2.5V.
Enabling the Outputs
The ENABLE pin turns on and turns off both outputs
of the iP1201PbF simultaneously. The iP1201PbF out-
puts will be turned off by pulling the ENABLE pin to V IN .
ENABLE low will start the outputs. The converter can
also be shutdown by pulling the soft-start pins to
PGND through a logic level MOSFET the drain of
which connects to the soft start pin (see Fig.14).
This feature can be useful if sequencing or different
start-up timing of the outputs are required. In situa-
tions where the output has undergone a latched shut-
down due to overvoltage or overcurrent, cycling
ENABLE will reset the outputs. Cycling soft start pins
will not unlatch the outputs.
Dual Soft Start
The Soft Start function provides a controlled rise of
the output voltage, thus limiting the inrush current
during start-up. The iP1201 PbF provides two indepen-
dent soft start functions. The soft start pins can be
connected to the soft start capacitors to provide
www.irf.com
Fig. 14: Soft Start/Enable Circuit
different start-up and sequencing profiles.
Each soft start function has an internal 25uA +/-20%
current source that charges the external soft start
capacitor C ss up to 3V. During power-up, the output
voltage starts ramping up only after the charging
voltage across the C ss capacitor has reached a
0.8Vtyp threshold, as shown in Fig. 15.
3V
0.8Vtyp
V Css
V OUT
Fig. 15: Power Up Threshold
This threshold voltage should be taken into consid-
eration when designing sequencing profiles using
the iP1201PbF as it will effect start-up delays and ramp-
times.
To ensure complete discharge of the soft start ca-
pacitor C ss, it is recommended to add a 1M ? resis-
tor directly across C ss .
For proper implementation of sequencing of out-
puts using the iP1201PbF, refer to IR Application Note
AN-1053 - Power sequencing techniques using
iP1201 and iP1202.
13
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