参数资料
型号: IP1202TR
厂商: International Rectifier
文件页数: 9/29页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 30A 198BGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 750
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 5 V
输入电压: 5.5 V ~ 13.2 V
频率 - 开关: 200kHz ~ 400kHz
电流 - 输出: 30A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 198-BGA(161 凸块)
包装: 带卷 (TR)
供应商设备封装: BGA(15.5x9.25)
iP1202
Pin Name
V IN
CC1
CC2
ENABLE
SS1
SS2
FB1
FB1s
FB2
FB2s
VSW1
VSW2
PGND
Vref
VP-ref
SYNC
R T
PGOOD
HICCUP
OCSET1
OCSET2
Ball Designator
A1 A2 A3 A4 A15 A16 A17 A18 B1 B2 B3 B4 B15 B16 B17
B18 C1 C2 C3 C4 C15 C16 C17 C18
H6
H13
A8 B8
H8
H11
J6
J8
J13
J11
D1 D2 D3 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2
D16 D17 D18 E17 E18 F17 F18 G17 G18 H17 H18 J17
J18 K17 K18 L17 L18
A5 A6 A7 A9 A10 A12 A13 A14 B5 B6 B7 B10 B11 B12
B13 B14 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D5 D6
D7 D8 D9 D10 D11 D12 D13 D14 E3 E4 E5 E6 E13 E14
E15 E16 F3 F4 F5 F6 F8 F9 F10 F11 F13 F14 F15 F16 G3
G4 G6 G9 G10 G13 G15 G16 H4 H9 H10 H15 J4 J5 J9
J10 J14 J15 K4 K5 K14 K15 L3 L4 L5 L13 L14 L15 L16
L9
L8
K6
L11
L10
L6
G8
G11
Pin Description
Input voltage connection pins
Output of the first error amplifier
Output of the second error amplifier
Single pin for both outputs. Commands ouputs ON or OFF. Normally
Pulled High. Pulled low, turns both outputs ON.
Soft start pin for output 1. External capacitor provides soft start.
Pulling soft start pin low will disable this output.
Soft start pin for output 2. External capacitor provides soft start.
Pulling soft start pin low will disable this output.
Inverting input of error amplifier 1
Output 1 overvoltage sense pin.
Inverting input of error amplifier 2
Output 2 overvoltage sense pin.
Output 1 inductor connection pins
Output 2 inductor connection pins
Power Ground pins
Amplifier 1 reference Voltage. Connect a 100pF cap from this pin to
PGND.
Amplifier 2 reference voltage. Connect to Vref for independent
output configuration. Refer to application notes on how to connect to
parallel configuration or output voltage tracking configurations.
External Clock synchronization pin. Set free running frequency to
80% of the SYNC frequency. When not in use, leave pin floating
Switching frequency setting pin. For R T selection, refer to Fig.9 of the
datasheet.
Power Good pin. Open collector, requires external pulll-up. If
function not needed, pin can be left floating
Logic level pin. Pulled high enables hiccup mode of operation. Pulled
low enables latched overcurrent shutdown mode.
Overcurrent trip threshold pin for output 1
Overcurrent trip threshold pin for output 2
Table 1: Pin Description
www.irf.com
9
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