参数资料
型号: IP1837TRPBF
厂商: International Rectifier
文件页数: 15/40页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 35A LGA
标准包装: 2,000
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 12 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 250kHz ~ 1.5MHz
电流 - 输出: 35A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-LLGA
包装: 带卷 (TR)
供应商设备封装: 17-LGA(7.65x7.65)
Highly ? Integrated ? 35A Single ‐ input ? Voltage, ??
Synchronous ? Buck ? Regulator ?
[V ]
iP1837
Vo
P re -B ia s
V o lta g e
[T im e ]
Figure ? 8: ? Pre ‐ Bias ? startup ?
At ? the ? end ? of ? the ? pre ‐ bias ? stage, ? the ? synchronous ? MOSFET ?
is ? switched ? complementary ? to ? the ? Control ? MOSFET. ??
?
Figure ? 8 ? shows ? a ? typical ? Pre ‐ Bias ? condition ? at ? start ? up. ?
Figure ? 7a: ? Normal ? Start ? up, ? Device ? turns ? on ??
when ? the ? Bus ? voltage ? reaches ? 10.2V ?
HDRv
...
LDRiss
...
...
...
...
...
Bus Voltage (12V)
12.5%
LDRv
...
25%
... ... ... ...
...
87.5%
32
32
32
End of
PB
?
Figure ? 9: ? Pre ‐ Bias ? startup ? pulses ??
PVcc(5V) or Vcc(3.3V)
Enable > 1.2V
SS
Figure ? 7b: ? Recommended ? startup ? sequence ??
?
SOFT ‐ START ?
The ? iP1837 ? has ? a ? programmable ? soft ‐ start ? to ? control ? the ?
output ? voltage ? rise ? and ? to ? limit ? the ? current ? surge ? at ? the ?
start ‐ up. ? To ? ensure ? correct ? start ‐ up, ? the ? soft ‐ start ?
sequence ? initiates ? when ? the ? Enable ? and ? Vcc ? rise ? above ?
their ? UVLO ? thresholds ? and ? generate ? the ? Power ? On ? Ready ?
(POR) ? signal. ? The ? internal ? current ? source ? (typically ? 20uA) ?
charges ? the ? external ? capacitor ? Css ? linearly ? from ? 0V ? to ? Vcc. ?
Figure ? 10 ? shows ? the ? waveforms ? during ? the ? soft ? start. ?
with ? Vcc ? or ? PVcc ??
The ? start ? up ? time ? can ? be ? estimated ? by: ?
PRE ‐ BIAS ? STARTUP ?
iP1837 ? is ? able ? to ? start ? up ? into ? pre ‐ charged ? output, ??
which ? prevents ? oscillation ? and ? disturbances ? of ? the ??
T start ?
? 0.8 - 0.2 ? * C SS
I ss
(1) ?
output ? voltage. ??
The ? output ? starts ? in ? asynchronous ? fashion ? and ? keeps ? the ?
synchronous ? MOSFET ? off ? until ? the ? first ? gate ? signal ? for ?
control ? MOSFET ? is ? generated, ? following ? which, ? the ?
synchronous ? MOSFET ? starts ? with ? a ? narrow ? duty ? cycle ? of ?
12.5% ? and ? gradually ? increases ? its ? duty ? cycle ? in ? steps ? of ?
12.5%, ? with ? 32 ? cycles ? at ? each ? step ? until ? the ? end ? of ? pre ‐ bias. ?
??
During ? the ? soft ? start ? the ? OCP ? is ? enabled ? to ? protect ? the ?
device ? for ? any ? short ? circuit ? and ? over ? current ? condition. ?
15
March ? 5, ? 2012 ?? | ?? V1.26 ???
97600
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