参数资料
型号: IP1837TRPBF
厂商: International Rectifier
文件页数: 24/40页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 35A LGA
标准包装: 2,000
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 12 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 250kHz ~ 1.5MHz
电流 - 输出: 35A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-LLGA
包装: 带卷 (TR)
供应商设备封装: 17-LGA(7.65x7.65)
Highly ? Integrated ? 35A Single ‐ input ? Voltage, ??
Synchronous ? Buck ? Regulator ?
iP1837
By ? replacing ? Z in ? and ? Z f ?? according ? to ? Figure ? 19, ? the ? transfer ?
Cross ? over ? frequency ? is ? expressed ? as: ?
( 1 ? sR 3 C 4 ) ? 1 ? sC 7 ? R 8 ? R 10 ? ?
H ( s ) ?
? ? ? ( 1 ? sR 10 C 7 )
sR 8 ( C 4 ? C 3 ) ? 1 ? sR 3 ? ?
F o ? R 3 * C 7 * V in * ? * F m *
(31) ?
function ? can ? be ? expressed ? as: ?
?
? ? C 4 * C 3 ? ?
? ?
? ? C 4 ? C 3 ? ?
.... (25)
?
1
2 ? * L o * C o
Based ? on ? the ? frequency ? of ? the ? zero ? generated ? by ? the ?
output ? capacitor ? and ? its ? ESR, ? relative ? to ? crossover ?
frequency, ? the ? compensation ? type ? can ? be ? different. ??
Z I N
V OSO
C 3
The ? table ? below ? shows ? the ? compensation ? types ? for ??
relative ? locations ? of ? the ? crossover ? frequency. ?
C 7
R 10
R 8
R 3
C 4
Z f
Compensator ?
Type ?
Type ? II ?
F ESR ? v/s ? F 0 ?
F LC ? < ? F ESR ? < ? F 0 ? < ? F S /2 ?
Output ?
Capacitor ?
Electrolytic ?
Tantalum ?
R 9
Fb
E/A
Comp
Ve
Tantalum ?
Type ? III ? F LC ? < ? F 0 ? < ? F ESR ?
Ceramic ?
The ? higher ? the ? crossover ? frequency, ? the ? potentially ? faster ?
Gain(dB)
H(s) dB
V REF
the ? load ? transient ? response ? will ? be. ? However, ? the ?
crossover ? frequency ? should ? be ? low ? enough ? to ? allow ?
attenuation ? of ? switching ? noise. ? Typically, ? the ? control ? loop ?
bandwidth ? or ? crossover ? frequency ? is ? selected ? such ? that: ?
F o ? ? 1/5 ~ 1/10 ? * F s ?
F Z 1
F Z 2
F P 2
F P 3
Frequency
Figure ? 19: ? Type ? III ? Compensation ? network ??
?
The ? DC ? gain ? should ? be ? large ? enough ? to ? provide ? high ??
DC ‐ regulation ? accuracy. ? The ? phase ? margin ? should ? be ?
greater ? than ? 45 o ? for ? overall ? stability. ?
and ? its ? asymptotic ? gain ? plot ?
For ? this ? design ? we ? have: ?
The ? compensation ? network ? has ? three ? poles ? and ? two ? zeros ?
and ? they ? are ? expressed ? as ? follows: ?
V in ? = ? 12V ?
V o ? = ? 1.8V ?
F P 1 ? 0
(26)
β? = ? V ref /V o =0.333 ??
Modulator ? gain ? = ? F m ? = ? 0.65, ? from ? Figure ? 15 ?
?
2 ? * R 3 ? ? 4
? ?
?
F P 2 ?
F P 3 ?
F Z 1 ?
F Z 2 ?
1
2 ? * R 10 * C 7
1
? C * C 3 ?
? C 4 ? C 3 ?
1
2 ? * R 3 * C 4
1
2 ? * C 7 * ( R 8 ? R 10 )
1
2 ? * R 3 * C 3
1
2 ? * C 7 * R 8
(27)
(28)
(29)
(30)
?
V ref ? = ? 0.6V ?
L o ? = ? 0.215uH ?
C o ? = ? 15x22uF, ? ESR ? = ? 3mOhm ? each ?
It ? must ? be ? noted ? here ? that ? the ? value ? of ? the ? capacitance ?
used ? in ? the ? compensator ? design ? must ? be ? the ? small ? signal ?
value. ? For ? instance, ? the ? small ? signal ? capacitance ? of ? the ?
22uF ? capacitor ? used ? in ? this ? design ? is ? 12uF ? at ? 1.8V ? DC ? bias ?
and ? 600kHz ? frequency. ? It ? is ? this ? value ? that ? must ? be ? used ? for ?
all ? computations ? related ? to ? the ? compensation. ? The ? small ?
signal ? value ? may ? be ? obtained ? from ? the ? manufacturer’s ?
datasheets, ? design ? tools ? or ? SPICE ? models. ? Alternatively, ?
they ? may ? also ? be ? inferred ? from ? measuring ? the ? power ? stage ?
transfer ? function ? of ? the ? converter ? and ? measuring ? the ?
double ? pole ? frequency ? F LC ? and ? using ? equation ? (16) ? to ?
compute ? the ? small ? signal ? C o . ?
24
March ? 5, ? 2012 ?? | ?? V1.26 ???
97600
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