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参数资料
| 型号： | IP1837TRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 19/40页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 35A LGA |
| 标准包装： | 2,000 |
| 系列： | iPOWIR™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 12 V |
| 输入电压： | 1.5 V ~ 16 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 250kHz ~ 1.5MHz |
| 电流 - 输出： | 35A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 17-LLGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 17-LGA（7.65x7.65） |
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Highly ? Integrated ? 35A Single ‐ input ? Voltage, ??
Synchronous ? Buck ? Regulator ?
iP1837
MINIMUM ? ON ? TIME ? CONSIDERATIONS ?
The ? minimum ? ON ? time ? is ? the ? shortest ? amount ? of ? time ? for ?
which ? the ? Control ? FET ? may ? be ? reliably ? turned ? on, ? and ? this ?
depends ? on ? the ? internal ? timing ? delays. ? For ? the ? iP1837, ??
the ? minimum ? on ‐ time ? is ? specified ? as ? 50 ? ns ? maximum. ??
Any ? design ? or ? application ? using ? the ? iP1837 ? must ? require ? a ?
pulse ? width ? that ? is ? at ? least ? equal ? to ? this ? minimum ? on ‐ time ?
and ? preferably ? higher ? than ? 100 ? ns. ? This ? is ? necessary ? for ? the ?
circuit ? to ? operate ? without ? jitter ? and ? pulse ‐ skipping, ? which ?
can ? cause ? high ? inductor ? current ? ripple ? and ? high ? output ?
voltage ? ripple. ?
MAXIMUM ? DUTY ? RATIO ? CONSIDERATIONS ?
For ? the ? iP1837, ? the ? upper ? limit ? on ? the ? operating ? duty ? ratio ?
is ? set ? by ? the ? duration ? of ? the ? PWMSet ? pulse ? or ? by ? the ? 200 ?
ns ? fixed ? off ‐ time, ? whichever ? is ? higher. ? Since ? the ? PWMSet ?
pulse ? has ? a ? 25% ? duty ? cycle, ? this ? limits ? the ? maximum ? duty ?
ratio ? at ? which ? the ? iP1837 ? can ? operate, ? to ? 75%. ? At ? switching ?
frequencies ? above ? 1.25 ? MHz, ? however, ? the ? maximum ? duty ?
ratio ? is ? set ? by ? the ? 200 ? ns ? fixed ? off ‐ time. ? Thus, ? at ? switching ?
frequencies ? above ? 1.25 ? MHz, ? higher ? the ? switching ?
frequency, ? the ? lower ? is ? the ? maximum ? duty ? ratio ? at ? which ?
the ? iP1837 ? can ? operate. ? Figure ? 13 ? shows ? a ? plot ? of ? the ?
maximum ? duty ? ratio ? v/s ? the ? switching ? frequency, ? with ? 200 ?
ns ? off ‐ time. ?
76%
75%
74%
73%
72%
71%
70%
69%
68%
67%
TRAILING ? EDGE ? PULSE ? WIDTH ? MODULATION ?
WITH ? RAMP ‐ SLOPE ? MODULATION ?
The ? iP1837 ? employs ? trailing ? edge ? Pulse ? width ? modulation. ?
However, ? unlike ? conventional ? trailing ? edge ? modulators, ?
which ? compare ? the ? PWM ? ramp ? with ? the ? output ? of ? the ?
error ? amplifier ? or ? the ? Comp ? voltage, ? in ? the ? modulation ?
scheme ? used ? in ? the ? iP1837, ? the ? slope ? of ? the ? PWM ? ramp ??
is ? modulated ? by ? the ? Comp ? voltage ? and ? this ? modulated ?
ramp ? is ? then ? compared ? to ? a ? fixed ? reference ? voltage. ??
The ? advantage ? of ? this ? scheme ? is ? that ? comparison ? always ?
takes ? place ? at ? a ? fixed ? reference ? irrespective ? of ? the ? duty ?
cycle ? of ? operation. ? Conventional ? modulators ? suffer ? from ?
increased ? noise ? susceptibility ? at ? the ? lower ? duty ? cycles, ?
since ? the ? comparison ? takes ? place ? at ? the ? Comp ? voltage ? level ?
which ? is ? close ? to ? the ? bottom ? of ? the ? PWM ? ramp ? for ? low ?
duty ? cycle ? operation. ?
Figure ? 14 ? shows ? theoretical ? waveforms ? for ? the ? PWM ? ramp ?
and ? the ? PWM ? output ? in ? response ? to ? a ? changing ? Comp ?
voltage. ? Figure ? 15 ? shows ? the ? variation ? of ? the ? modulator ?
gain ? (F m ) ? with ? the ? duty ? cycle ? (D). ?
? Figure ? 14: ? Theoretical ? waveforms ? for ? the ? new ? PWM ? scheme ?
?
66%
250
350
450
550
650
750
850
950 1050 1150 1250 1350 1450 1550 1650
Modulator Gain = -2E-05D 2 + 0.0156D + 0.4168
Switching Frequency (kHz)
?
1.4
? Figure ? 13: ? Maximum ? duty ? cycle ? v/s ? switching ? frequency. ?
1.2
1
0.8
0.6
0.4
0.2
0
5
10
15
20
25
30
35
40
45
50
55
D(%)
? Figure ? 15: ? Modulator ? gain ? (F m ) ? v/s ? Duty ? Ratio ? (D%) ?
?
19
March ? 5, ? 2012 ?? | ?? V1.26 ???
97600
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