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参数资料
| 型号： | IP82C89 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 外设及接口 |
| 英文描述： | CMOS Bus Arbiter |
| 中文描述： | 8 MHz, BUS ARBITER AND CONT SIG GEN, PDIP20 |
| 文件页数： | 8/15页 |
| 文件大小： | 123K |
| 代理商： | IP82C89 |
4-350
FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION
NOTE: By adding another 82C89 arbiter and connecting its AEN to the 82C88 whose AEN is presently grounded, the processor could have
access to two multi-master buses.
TRANSCEIVER
82C86H/
82C87H
(2)
T
OE
IOB
AEN
82C89
BUS
ARBITER
S0
S1
S2
CLK
ANYRQST
SYSB/
RESB
82C84A/85
CLOCK
RDY2
READY
AEN2
RDY1
CLK
80C86
CPU
READY
S0-S2
AD0-AD15
A16-A19
CLK
AEN1
RESB
DEN
82C88
CLK
S0-S2
IOB
ALE
DT/R
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
OE
STB
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
OE
STB
TRANSCEIVER
82C86H/
82C87H
(2)
OE
T
DEN
82C88
CLK
S0-S2
ALE
DT/R
AEN
PROM
OR
DECODER
OR
CMOS HPL
(NOTE)
CEN
STATUS
AEN
CEN
V
CC
XACK MULTI MASTER
SYSTEM BUS
MULTI MASTER
SYSTEM BUS CONTROL
MULTI MASTER
SYSTEM COMMAND BUS
MULTI MASTER
SYSTEM ADDRESS BUS
MULTI MASTER
SYSTEM DATA BUS
XACK
RESIDENT BUS
RESIDENT
COMMAND BUS
RESIDENT
ADDRESS BUS
RESIDENT
DATA BUS
R
M
82C89
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