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| 型号： | IPR-VITERBI/HS |
| 厂商： | Altera |
| 文件页数： | 43/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI HIGH-SPEED RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 高速编译器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
Signals
Table 3–10. Configuration Signals (Part 2 of 2)
Signal Name
Description
3–17
Selects the codeword—’0’ selects the first codeword, ‘1’ selects the second,
sel_code[log2(Ncodes):1]
tb_length[]
tb_type
tr_init_state[(L-1):1]
and so on. The bus size increases according to the number of codes
specified. sel_code is latched when sink_sop is asserted.
Traceback length. The maximum width of tb_length is equal to the
maximum value of parameter v . The tb_length input is latched when
sink_sop is asserted. This signal is disabled if you select the continuous
optimization and you must remove it from the testbench.
Altera recommends that you set tb_type high always for future
compatibility. In block decoding when tb_type is low, the decoder starts
from state 0; when tb_type is high, the decoder uses the state specified in
tr_init_state[(L-1):1] . For block decoding set tb_type high.
tb_type is latched when sink_eop is asserted. If you select continuous
optimization, this input is removed from the top level design and connected
to zero in the inner core.
Specifies the state to start the traceback from, when tb_type is asserted
high. tr_init_state is latched when sink_eop is asserted. If you select
continuous optimization, this input is removed from the top level design and
connected to zero in the inner core. For more information, refer to “Trellis
Termination” on page 3–8 .
Specifies the state in which to initialize with the value from the
bm_init_state[(L-1):1]
bm_init_value[(L-1):1]
(1)
(1)
bm_init_value[] bus. All other state metrics are set to zero.
bm_init_state is latched when sink_sop is asserted.
Specifies the value of the metric that initializes the start state. All other
metrics are set to 0. bm_init_value must be larger than
( L × 2 (softbits – 1) ). bm_init_value is latched when sink_sop is asserted.
Note to Table 3–10 :
(1) Hybrid architecture only.
Table 3–11 shows the status signals.
Table 3–11. Status Signals (Part 1 of 2)
Signal
normalizations[8:1]
Description
The normalizations bus indicates in real time the number of normalizations that have
occurred since sink_sop was last activated. (Refer to “State Metrics” on page 3–2 .)
The numerr bus contains the number of errors detected during a block. It is updated
each time an error is detected, so you can see the location of individual errors. It is reset
numerr[]
(1)
when source_sop asserted; it is valid two-clock cycles after source_sop . IP Toolbench
automatically sets the width of this bus. This signal is left open if you do not select a
BER block.
The best metric. The bestmet signal shows the best state metric for every trellis step as
bestmet[bmgwide:1]
it is being found by the best state finder. The state that contains this best metric is
shown in bestadd . This signal is left open, if you select continuous optimization, or if
you select none for optimization and turn off best state finder in IP Toolbench.
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-XAUIPCS | 功能描述:开发软件 10G Ethernet Phy MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPS0151 | 功能描述:IC MOSFET PWR SWITCH TO-220AB RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 内部开关 系列:- 标准包装:1,000 系列:- 类型:高端/低端驱动器 输入类型:SPI 输出数:8 导通状态电阻:850 毫欧，1.6 欧姆 电流 - 输出 / 通道:205mA，410mA 电流 - 峰值输出:500mA，1A 电源电压:9 V ~ 16 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:PG-DSO-20-45 包装:带卷 (TR) |
| IPS0151PBF | 制造商:International Rectifier 功能描述:MOSFET SMART SWITCH TO-220 |
| IPS0151S | 功能描述:IC MOSFET PWR SWITCH D2PAK RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 内部开关 系列:- 标准包装:1,000 系列:- 类型:高端/低端驱动器 输入类型:SPI 输出数:8 导通状态电阻:850 毫欧，1.6 欧姆 电流 - 输出 / 通道:205mA，410mA 电流 - 峰值输出:500mA，1A 电源电压:9 V ~ 16 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:PG-DSO-20-45 包装:带卷 (TR) |
| IPS0151S | 制造商:International Rectifier 功能描述:MOSFET SMART SWITCH D2-PAK |
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