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| 型号： | IQ32B-TQ52 |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | CROSSBAR SWITCH, PQFP52 |
| 封装： | PLASTIC, TQFP-52 |
| 文件页数： | 27/31页 |
| 文件大小： | 620K |
| 代理商： | IQ32B-TQ52 |
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IQ Family Data Sheet
January 1999
5
1.0 ARCHITECTURE
The IQ devices are designed using 0.6 m CMOS technology
and are congured by storing appropriate data into the internal
SRAM cells and registers. The main functional blocks of the
device are the Switch Matrix (Crossbar Array), I/O Ports, and
Conguration Controller (see Figure 1).
External signals enter and exit each device through its I/O Ports.
The Switch Matrix is used to internally connect these I/O Ports to
one another.
The JTAG-based Conguration Controller decodes the incoming
conguration bitstream and stores the data into the Switch Matrix
SRAM cells and I/O Port conguration registers. Additionally, by
enabling the RapidConnect mode, the SRAM cells can be
accessed directly, allowing incremental changes (make or break)
to the Switch Matrix connections in a single cycle.
1.1 Switch Matrix
Figure 2 shows a small section of the Switch Matrix.
Figure 2. Switch Matrix (Crossbar Array) Structure
The Switch Matrix consists of a number of signal lines, one per
I/O Port, and an array of pass transistor switches, each
programmable with an SRAM cell. Each switch, when
programmed to be in the ON state, connects a unique pair of
signal lines in the Switch Matrix. The external signals are
connected to the Switch Matrix signal lines through I/O Ports.
A connection between two I/O Ports is made by turning ON the
transistor switch at the intersection of the corresponding signal
lines. The Switch Matrix is globally connected, and therefore a
connection can always be made between any two I/O Ports.
Moreover, only one transistor switch needs to be turned ON in
order to make a connection between two I/O Ports. This
arrangement provides a fully non-blocking architecture offering
100% utilization, guaranteed connections, and uniform and
predictable delays.
This Switch Matrix architecture supports connecting more than
two I/O Ports together for multicasting/broadcasting operation. A
new connection can be made or an existing connection can be
broken without affecting other connections, allowing incremental
reconguration of the Switch Matrix.
The contents of the SRAM cells controlling the pass transistor
switches are unchanged when the device is reset. The SRAM
cells must be explicitly cleared during initialization to eliminate
any residual connections.
1.2 Programmable I/O Ports
The I/O Port structure is shown in Figure 3.
Figure 3. Programmable I/O Buffer
The attributes of each I/O Port are individually programmable.
The attributes include its I/O function, output voltage level and
pull-up current. Each I/O Port is buffered to provide high input
impedance, low input capacitance, low output impedance and
high current drive.
The IQ devices, with the exception of IQ48 and IQ32B, have four
Output Enable signals, each controlling an equal number of I/O
Ports; 80 each in the case of IQ320, 60 each for IQ240B and so
on. The IQ48 and IQ32B have a single Output Enable signal that
controls all I/O Ports. All IQ devices have two global clock
signals, ICLK and OCLK.
1
0
2
34
567
I/O Port Pins
SRAM
Cells
Pass
Transistors
Signal
Lines
Programmable I/O Buffers
Permanent
Connections
I/O Port
BR
Pull-Up
Current
TTL/CMOS
Voltage
NB
NC
ICLK
OE
OCLK
Switch
Matrix
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