参数资料
型号: IR3084UMPBF
厂商: International Rectifier
文件页数: 18/47页
文件大小: 0K
描述: IC XPHASE CONTROL 28-MLPQ
标准包装: 100
系列: XPhase™
应用: 处理器
电流 - 电源: 14mA
电源电压: 9.5 V ~ 16 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 28-MLPQ
供应商设备封装: 28-MLPQ(5x5)
包装: 剪切带 (CT)
IR3084U
Dynamic VID Operation
The IR3084U can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amp is programmed by the external resistor that sets the oscillator
frequency (Rosc). The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between
VDAC pin and the VOSNS? pin. A resistor connected in series with this capacitor is required to compensate the
VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and
converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output
voltage.
Adaptive Voltage Positioning (AVP)
Adaptive Voltage Positioning (AVP) is needed to reduce the total output voltage deviations during load transients
and to reduce the power dissipation of the load when it is drawing high current. The circuitry related to the voltage
positioning is shown in Figure 8.
Resistor R SETPT is connected between the VDAC pin and the VSETPT pin to set the desired amount of fixed
offset voltage above or below the DAC voltage. The VSETPT pin is internally connected to both the non-inverting
input of the voltage error amplifier and an internal current source, I OFFSET . The magnitude of I OFFSET is
programmed by the external resistor that programs the oscillator frequency (Rosc) while the polarity of I OFFSET is
set by the VIDSEL pin. When the VR10 and VR11 DAC tables are selected, the polarity of I OFFSET is positive
(current flows into the pin). When the Opteron/Athlon64 DAC table is selected, the polarity of I OFFSET is negative
(current flow out of the pin). The voltage across RSETPT sets the no load offset voltage above or below the
VDAC voltage.
The voltage at the VDRP pin is a buffered version of the current share bus (Iin) and represents the sum of the
VDAC voltage and the average inductor current of all the phases. The VDRP pin should be connected to the FB
pin through the resistor RDRP. Because the Error Amp will regulate the voltage at the FB pin equal to the
voltage at the VSETPT pin, a current will flow from the VDRP pin to the FB pin equal to (VDRP?VSETPT) / R DRP .
When the load current increases, the VDRP voltage will increase, additional current will flow through the
feedback resistor R FB and the converter’s output voltage will droop below the no load setpoint. The amount of
voltage droop can be programmed by the resistor R DRP so the converter’s output impedance meets the load-line
specification set by the CPU manufacturer. The offset and slope of the converter’s output impedance are
referenced to VDAC and are therefore independent of the exact VDAC (VID) setting.
Due to the difference between VDAC and FB, the voltage at the VDRP pin causes additional offset voltage
through RDRP and RFB. The total offset voltage is the sum of the voltage across RVSETPT and the voltage
drop across the RFB resistor at no load.
Control IC
VDAC
VDAC
Phase IC
VSETPT
EAOUT
RSETPT
ISHARE
VDAC
10k
Current Sense
Amplifier
CSIN+
CSIN-
IOFFSET
Error
Amplifier
VDRP
FB
RFB
RDRP
Vo
Amplifier
VDRP
Phase IC
Current Sense
-
+
IIN
ISHARE
Amplifier
CSIN+
CSIN-
VDAC
10k
Figure 8 - Adaptive voltage positioning
Page 18 of 47
June 1, 2009
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