参数资料
型号: IR3092MTR
厂商: International Rectifier
英文描述: 2 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC
中文描述: 2相皓龙,速龙,或控制IC的VR10.X
文件页数: 23/37页
文件大小: 619K
代理商: IR3092MTR
IR3092
Page 23 of 37
06/25/04
Measure the inductance L and the inductor DC resistance R
L
. Pre-select the capacitor C
CS
and calculate R
CS
as follows.
R
L
R
CS
L
CS
C
(11)
The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across R
CS,
which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of converter
current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted.
To reduce the offset voltage, a resistor R
CSO
should be added between the amplifier inverting input and the converter
output, as shown in Fig1
.
The
resistor R
CSO
is determined by the ratio of the bias current from the non-inverting input and
the bias current from the inverting input.
I
R
CS
CSIN
CSIN
CSO
R
I
(12)
If R
CSO
is not used, R
CS
should be chosen so that the offset voltage is small enough. Usually R
CS
should be less than 2
k
DQG WKHUHIRUH D ODUJHU &
CS
value is needed.
Inductor DCR Temperature Correction
If the Current Sense Amplifier temperature dependent gain is not adequate to compensate the inductor DCR TC, a
negative temperature coefficient (NTC) thermistor can be added. The thermistor should be placed close to the inductor
and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is
used to reduce the nonlinearity of the thermistor.
Figure 10- Temperature compensation of inductor DCR
Remote Voltage Sensing
To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects directly to
the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a separate
differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed transients are fed
directly into the Error Amplifier without delay.
Master-Slave Current Share Loop
Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The output
of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifier. The Share Adjust Error
Amplifier will then adjust the duty cycle of PWM Ramp2 to force its input error to zero, resulting in accurate current
sharing.
VDRP BUFFER
+
IROSC
-
+
ERROR AMPLIFIER
-
VDAC
RFB
RDRP
VDAC
EAOUT
VDRP
VOSNS-
FB
VOUT SENSE+
Current + VDAC
RLINEAR
RNTC
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