参数资料
型号: IR3500AMPBF
厂商: International Rectifier
文件页数: 8/48页
文件大小: 0K
描述: IC CTRL XPHASE3 VR11.0 32-MLPQ
标准包装: 100
系列: XPhase3™
应用: 处理器
电流 - 电源: 6.5mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 管件
IR3500A
PIN DESCRIPTION
PIN#
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN SYMBOL
VID7-0
ENABLE
VRHOT
HOTSET
VOSEN-
VOSEN+
VO
FB
EAOUT
VDRP
IIN
VSETPT
OCSET
VDAC
SS/DEL
ROSC/OVP
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
VCCLFB
VCCLDRV
VRRDY
VIDSEL
Page 8 of 48
PIN DESCRIPTION
Inputs to VID D to A Converter.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin
as the logic state will be undefined.
Open collector output of the VRHOT comparator which drives low if HOTSET pin voltage is
lower than 1.6V. Connect external pull-up.
A resistor divider including thermistor senses the temperature, which is used for VRHOT
comparator.
Remote sense amplifier input. Connect to ground at the load.
Remote sense amplifier input. Connect to output at the load.
Remote sense amplifier output.
Inverting input to the error amplifier.
Output of the error amplifier.
Buffered IIN signal. Connect external RC network to FB to program converter output
impedance.
Average current input from the phase IC(s). This pin is also used to communicate over
voltage condition to phase ICs.
Error amplifier non-inverting input. Converter output voltage can be decreased from the
VDAC voltage with an external resistor connected between VDAC and this pin (there is an
internal sink current at this pin).
Programs the constant converter output current limit and hiccup over-current thresholds
through an external resistor tied to VDAC and an internal current source from this pin.
Over-current protection can be disabled by connecting a resistor from this pin to VDAC to
program the threshold higher than the possible signal into the IIN pin from the phase ICs
but no greater than VCCL – 2V (do not float this pin as improper operation will occur).
Regulated voltage programmed by the VID inputs. Connect external RC network to LGND
to program dynamic VID slew rate and provide compensation for the internal buffer amp.
Programs converter startup and over current protection delay timing. It is also used to
compensate the constant output current loop during soft start. Connect an external
capacitor to LGND to program.
Connect a resistor to LGND to program oscillator frequency and OCSET, VSETPT and
VDAC bias currents. Oscillator frequency equals switching frequency per phase. The pin is
0.6V during normal operation and higher than 1.6V if over-voltage condition is detected.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of
phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first
phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a
decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator
is programmed by the resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control external transistor. The pin senses
12V power supply through a resistor.
Open collector output that drives low during startup and under any external fault condition.
Connect external pull-up.
The pin configures VIDs for AMD 6-bit, Intel VR11 8-bit with 1.1V Boot voltage, Intel VR11
8-bit without 1.1V Boot voltage or AMD 5-bit Opteron.
July 28, 2009
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