参数资料
型号: IR3502MTRPBF
厂商: International Rectifier
文件页数: 9/39页
文件大小: 0K
描述: IC XPHASE3 CONTROLLER 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
产品目录页面: 1383 (CN2011-ZH PDF)
其它名称: IR3502MTRPBFDKR
IR3502
SYSTEM THEORY OF OPERATION
System Description
The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The
control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three
analog buses, i.e., VDAC, EA, IIN. The digital buses are responsible for switching frequency determination and
accurate phase timing control without any external component. The analog buses are used for PWM control and
current sharing among interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK
signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by
each phase of the converter, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, Phase
disable circuit, current sensing and sharing, etc.
CONTROL IC
GATE DRIVE
VOLTAGE
PHSOUT
VIN
PHASE IC
VCC
CLOCK GENERATOR
CLKOUT
CLKIN
CLK Q
D
VCCH
PHSOUT
PHSIN
PHSIN
EAIN
1
PWM
COMPARATOR
-
+
2
RESET
U246
DOMINANT
D Q
CLK Q
DFFRH
VID6
OFF
GATEH
SW
VCCL
CBST
COUT
VOSNS+
VOUT
PWM LATCH
GND
REMOTE SENSE
AMPLIFIER
VO
ENABLE
VID6
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
VID6
OFF
GATEL
PGND
VOSNS-
CLAMP
VDAC
LGND
SHARE ADJUST
ERROR AMPLIFIER
PSI
PSI
VDAC
ERROR
AMPLIFIER
EAOUT
RCOMP
RFB1
RFB
ISHARE
3K
-
VID6
VID6
+
VID6
VID6 +
CURRENT
SENSE
AMPLIFIER
CSIN+
CCS
RCS
+
CSIN-
FB
RVSETPT
CCOMP
CFB
RDRP1
DACIN
PHSOUT
IVSETPT
IROSC
VSETPT
IMON
CDRP
RDRP
CLKIN
CLK Q
PHASE IC
VCC
VDAC
D
1
2
RESET
U248
DOMINANT
VCCH
VDRP
AMP
Thermal
Compensation
VDRP
VN
PHSIN
EAIN
PWM
COMPARATOR
-
+
D Q
CLK Q
DFFRH
VID6
OFF
GATEH
SW
CBST
RTHRM
ENABLE
PWM LATCH
VCCL
IIN
VID6
BODY
GATEL
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
BRAKING
COMPARATOR
VID6
OFF
PGND
PSI
PSI
ERROR AMPLIFIER
CURRENT
ISHARE
3K
-
VID6
VID6
+
SENSE
AMPLIFIER
CSIN+
VID6
VID6 +
+
DACIN
Figure 3 System Block Diagram
CSIN-
CCS
RCS
The PWM block diagram of the XPhase3
PWM Control Method
TM
architecture is shown in Figure 3. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the control IC and the system clock frequency is programmable from 250kHz to 9MHZ by
an external resistor. The control IC system clock signal CLKOUT is connected to CLKIN of all the phase ICs. The
phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output PHSOUT is
Page 9 of 39
July 28, 2009
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