参数资料
型号: IR3504MTRPBF
厂商: International Rectifier
文件页数: 2/42页
文件大小: 0K
描述: IC CTRL XPHASE3 SVID 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
IR3504
APPLICATION CIRCUIT
12V
Q1
12V
VCCL
To Converters
To Phase IC
RVCCLDRV
RVCCLFB1
RVCCLFB2
CVCCL
VCCL & GATE
DRIVE BIAS
Phase Clock Input to
Power Good
SVC
PHSIN
PHSOUT
CLKOUT
Last Phase IC of VDD
2 wire
Digital
Daisy Chain
Bus to VDD
& VDDNB
SVD
PWROK
1
2
SVD
PWROK
LGND
ROSC
24
23
ROSC
Phase ICs
5
7
ENABLE
CVDAC2
3
4
CSS/DEL2
RVDAC2
6
ROCSET2
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
IR3504
CONTROL
IC
VDRP1
IIN1
SS/DEL1
VDAC1
OCSET1
22
21
20
19
18
RVDAC1
ROCSET1
CSS/DEL1
CVDAC1
ISHARE1
VDAC1
3 Wire Analog
Control Bus
to VDD Phase
8
EAOUT2
EAOUT1
17
CDRP1
EAOUT1
ICs
RDRP1
RCP2
CCP21
RFB22
CFB2
CFB1
RFB12
RCP1
CCP11
Load Line NTC
Thermistor;
CCP22
RFB21
RFB11
CCP12
RTHERMISTOR1
Locate close to
VDD Power Stage
RFB13
VDD SENSE +
VDD SENSE -
To VDD
Remote
Sense
EAOUT2
VDAC2
ISHARE2
3 Wire Analog
Control Bus to
VDDNB Phase
ICs
VDDNB SENSE -
VDDNB SENSE +
To VDDNB
Remote
Sense
Figure 1 – IR3504 Application Circuit
PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
PIN SYMBOL
SVD
PWROK
ENABLE
IIN2
SS/DEL2
VDAC2
OCSET2
PIN DESCRIPTION
SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output
for both master (AMD processor) and slave (IR3504), requires an external bias
voltage and should not be floated
System wide Power Good signal and input to the IR3504. When asserted, the
IR3504 output voltage is programmed through the SVID interface protocol.
Connecting this pin to VCCL enables VFIX mode.
Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high
on the pin enables the converter and causes the SVC and SVD input states to be
decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic
state will be undefined.
Output 2 average current input from the output 2 phase IC(s). This pin is also used
to communicate over voltage condition to the output 2 phase ICs.
Programs output 2 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
Output 2 reference voltage programmed by the SVID inputs and error amplifier non-
inverting input. Connect an external RC network to LGND to program dynamic VID
slew rate and provide compensation for the internal buffer amplifier.
Programs the output 2 constant converter output current limit and hiccup over-
current threshold through an external resistor tied to VDAC2 and an internal current
source from this pin. Over-current protection can be disabled by connecting a
resistor from this pin to VDAC2 to program the threshold higher than the possible
signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this
pin as improper operation will occur).
Page 2
July 28, 2009
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