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| 型号： | IR3519STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET GATE DRIVER SON-8 |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 15ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 35V |
| 电源电压： | 7V |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SON |
| 包装： | 带卷 (TR) |
IR3519
C B = C g ? ? ? B
? 1 ? ?
FUNCTIONAL DESCRIPTION
IR3519 switches the LGATE and UGATE signals
when VDD is greater than V UVLO and EN/UV voltage
is greater than V EN TH .
The gate drive logic features adaptive dead time
which prevents simultaneous conduction of the upper
and lower MOSFETs. The lower gate voltage must
be below approximately 1V after PWM goes HIGH
and before the upper MOSFET can be gated on. Also
the upper gate voltage, the different voltage between
UGATE and PH, must be below approximately 1V
after PWM goes LOW and before the lower MOSFET
can be gated on.
The internal logic will evaluate the PWM voltage
level. The PWM is considered HIGH when its level is
greater than V UGATE TH . PWM is considered LOW
when its level is below V LGATE TH . In the middle
voltage region of V UGATE TH and V LGATE TH , the PWM
will be in tri-state mode. In the absence of external
drive, the PWM pin is pulled to this middle region by
a V PWM TRI source through an internal resistor. After a
short time delay in this middle region, IR3519 is
forced into a low power state.
The UGATE logic evaluates its input logic signal and
generates a PH referenced to drive the UGATE pin,
which turns on/off the external high side MOSFET.
PH pin is to be connected to the source of the upper
MOSFET, the buck inductor, and to the drain of the
lower MOSFET. To turn on the upper N channel
MOSFET, a bootstrap circuit is required. This is
accomplished by charging a capacitor (connected
BOOT to PH) after the lower MOSFET conducts and
the PH pin is substantially at GND. VDD provides the
charging current through an internal BOOTSTRAP
diode. The minimum boot capacitor value is
calculated below.
The boot capacitor starts the cycle fully charged to a
voltage of V B (0). An equivalent gate drive
capacitance is calculated by consulting the high side
MOSFET data sheet and taking the ratio of total gate
charge at the VDD voltage, Q G (VDD), to the VDD
voltage. Q G (VDD)/VDD is the equivalent gate drive
capacitance C g which will be used in the following
calculations. The voltage of the capacitor pair C B and
C g after C g becomes charged at C B ’s expense will be
V B (0)- Δ V. Choose a sufficiently small Δ V such that
V B (0)- Δ V exceeds the maximum gate threshold
voltage to turn on the high side MOSFET. Since total
charge Q T is conserved, we can write the following
equation.
V B (0) ? C B = Q T = V(t on ) ? (C B + C g )
After rearranging this equation, it becomes the
equation below.
? V (0) ?
? Δ V ?
Choose a boot capacitor value larger than the
calculated C B . The voltage rating of this part needs to
be larger than V B (0) plus the desired derating
voltage. Its ESR and ESL needs to be low in order to
allow it to deliver the large current and di/dt’s which
drive MOSFETs most efficiently. In support of these
requirements a ceramic capacitor should be chosen.
The LGATE logic evaluates its input signal and
generates a GND referenced to drive the LGATE pin,
which turns on/off the external low side MOSFET.
The LGATE logic uses VDD source to turn on the low
side MOSFET because the source of low side
MOSFET is reference to GND.
LAYOUT RECOMMENDATION
One 1uF high quality ceramic capacitor is required to
place near VDD pin as possible. Other end of
capacitor is recommended to tie to GND pin plan as
close to as IC possible. This GND island plan can be
via or directly connect to the main GND plan or layer.
If the connection of GND pin to the source of low side
MOSFET through an internal layer, it is
recommended connecting through at least 2 vias by
build a small island of next to GND pin. The boot
capacitor needs to place close to BOOT and PH pins
to reduce the impedance during the turn-on process
of high side MOSFET. The main function of boot
capacitor is to supply the energy for turning on high
side MOSFET. It is recommended to add zero Ohm
resistor in series with boot capacitor as place holder.
When connecting the trace for UGATE and LGATE
signals, one needs to keep in mind that the signal
return path is as an important as signal path.
The return path contains both AC and DC current.
DC current takes the least resistance path. AC
current takes the least impedance path. The return
path is exits whether or not provide it. If the designer
is overlooked the return path, the AC current will
cause the more noise in the system. Therefore, it is
recommended to place LGATE signal path on top
next to the source of low side MOSFET path and
place UGATE signal path on top of PH signal path.
When connecting PHASE signal path to power stage
area, PHASE signal needs to chose quite area.
Figure 1 shows the location of connection from power
stage to IR3519 PHASE pin less noise sensitive than
Figure 2.
Page 7 of 10
www.irf.com
8/15/08
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