参数资料
型号: IR3623MTRPBF
厂商: International Rectifier
文件页数: 20/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32MLPQ
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.2MHz
占空比: 85%
电源电压: 8.5 V ~ 14.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 标准包装
其它名称: IR3623MTRPBFDKR
IR3623MPbF
Feedback Compensation
The IR3623 is a voltage mode controller; the
control loop is a single voltage feedback path
V OUT
R 6 F b
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
R 5
V REF
E/A
Comp
C 9
R 4
Ve
C POLE
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45 o ).
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180 o
Gain(dB)
H(s) dB
(see figure 18). The resonant frequency of the LC
filter expressed as follows:
F Z
Frequency
F LC ?
1
2 ? ? L o ? C o
- - - -(15)
Fig. 19: TypeII compensation network
and its asymptotic gain plot
figure 16 shows gain and phase of the LC filter.
Since we already have 180 o phase shift just from
the output filter, the system risks being unstable.
The transfer function (Ve/Vo) is given by:
H ( s ) ? ? ? g m *
R 5 ? 1 ? sR 4 C 9
R 5 ? R 6 ? ?
?
?
? *
sC 9
- - - -(17)
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
? H ? s ? ? ? ? ? ? g m *
? * R 4
Fig. 18: Gain and Phase of LC filter
?
R 5 ?
R 5 ? R 6 ? ?
- - - -(18)
The IR3623’s error amplifier is a differential-input
transconductance amplifier. The output is
F z ?
1
2 ? * R 4 * C 9
- - - -(19)
available for DC gain control or AC phase
compensation.
The E/A can be compensated either in type II or
typeIII compensation. When it is used in typeII
compensation the transconductance properties of
the E/A become evident and can be used to
cancel one of the output filter poles. This will be
accomplished with a series RC circuit from Comp
The gain is determined by the voltage divider and
E/A’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
F o ? F ESR and F o ? ? 1/5 ~ 1/10 ? * F s
Use the following equation to calculate R 4 :
V in * F LC * R 5 * g m
pin to ground as shown in figure 19.
This method requires that the output capacitor
should have enough ESR to satisfy stability
R 4 ?
V osc * F o * F ESR * ( R 5 ? R 6 )
2
- - - -(20)
F ESR ?
2 ? ? * ESR * C o
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin. The ESR zero of the output capacitor
expressed as follows:
1
- - - -(16)
Where:
V in = Maximum Input Voltage
V osc = Oscillator Ramp Voltage
F o = Crossover Frequency
F ESR = Zero Frequency of the Output Capacitor
F LC = Resonant Frequency of the Output Filter
g m = Error Amplifier Transconductance
www.irf.com
January 28, 2013
20
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