参数资料
型号: IR3623MTRPBF
厂商: International Rectifier
文件页数: 23/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32MLPQ
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.2MHz
占空比: 85%
电源电压: 8.5 V ~ 14.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 标准包装
其它名称: IR3623MTRPBFDKR
IR3623MPbF
Compensation for Current Loop
(slave channel)
The slave error amplifier is differential
transconductance amplifier, in 2-phase
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
match the master channel inductor current as
Select a zero frequency for current loop (F o2 )
1.25 times larger than zero cross frequency for
voltage loop (F o1 ).
F O 2 ? 1 . 25 % * F O 1
well provides highest bandwidth and adequate
phase margin for overall stability. The following
analysis is valid for both using external current
H ( F O 2 ) ? g m * R s 1 * R 2 *
V in
2 ? * F O 2 * L 2 * V osc
? 1
- - - - ( 25 )
sense resistors and using DCR of inductor.
The transfer function of power stage is
expressed by:
From (25), R2 can be expressed as:
G ( s ) ?
I L 2 ( s )
V e
?
V in
sL 2 * V osc
- - - - ( 23 )
R 2 ?
1
g m * R s 1
*
2 ? * F O 2 * L 2 * V osc
V in
- - - - ( 26 )
Where:
V in =Input voltage
L 2 =Output inductor
V osc =Oscillator Peak Voltage
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (24), when using a
series RC circuit as shown in figure21.
I L2
V in =13.2V
V osc =1.25V
g m =2800umoh
L 2 =0.34uH
R s1 =DCR=1.1mOhm
F o2 =125kHz
This results to : R 2 =8.2K
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Fb2
L 2
F P ?
R eq
2 ? * L 2
R S2
Vp2
E/A2
Comp2
Ve
Where R eq is the total resistance of the power
R S1
L 1
R 2
C 2
stage which includes the R ds(on) of MOSFET
switches, the DCR of inductor and shunt
resistance (if it used).
I L1
Fig. 21: The Compensation network for current loop
R eq ? R ds ( on ) ? R L ? R s
R eq =9.4mOhm
Set the zero of compensator at 10 times the
? ? ? g m * s 1 ? ? * ? ?
? ?
D ( s ) ?
V e ( s )
R s 2
? R ? ? 1 ? sC 2 R 2 ?
? R s 2 ? ? sC 2 ?
- - - - ( 24 )
dominant pole frequency F P , the compensator
capacitor, C2 can be expressed as:
C 2 ?
The loop gain function is:
H ( s ) ? ? G ( s ) * D ( s ) * R s 2 ?
F z ? 10 * F P
1
2 ? * R 2 * F z
H ( s ) ? R s 2 * ? ? g m * s 1 ? ? * ? ?
? ? * ? ?
?
? R ? ? 1 ? sR 2 C 2 ? ?
? R s 2 ? ? sC 2 ? ?
V in ?
sL 2 * V osc ? ?
C 2 =0.47nF
All design should be tested for stability to verify
the calculated values.
www.irf.com
January 28, 2013
23
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