参数资料
型号: IR3640MPBF
厂商: International Rectifier
文件页数: 12/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-MLPQ
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.65MHz
占空比: 92%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 管件
IR3640MPBF
An over-current detection trips the OCP
comparator, latches OCP signal and cycles
the soft start function in hiccup mode.
The hiccup is performed by shorting the soft-
start capacitor to ground and counting the
number of switching cycles. The soft start pin
is held low until 4096 cycles have been
completed. The OCP signal resets and the
converter recovers. After every soft start cycle,
the converter stays in this mode until the
overload or short circuit is removed.
The OCP circuit starts sampling current
typically 160 ns after the low gate drive rises
to about 3V. This delay functions to filter out
switching noise.
The value of R OCSet should be checked in an
actual circuit to ensure that the over current
protection circuit activates as expected.
Shutdown
Vo1
Vo2
Simultaneous Powerup
Fig. 9a: Simultaneous Power-up of the slave
with respect to the master.
Through these pins, voltage sequencing such as
simultaneous, sequential, etc. can be
implemented. Figure 9b shows simultaneous
sequencing configurations. In simultaneous
powerup, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
R E /R F =R C /R D , therefore, the output voltage of
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
Vin1
Vcc
The IR3640 can be shutdown by pulling the
Enable pin below its 1 V threshold. This will tri-
state both, the high side driver as well as the
PGood1
Vcc
PGood
Enable
Boot
HDrv
SW
OCSet
Vo (Master)
low side driver. Alternatively, the output can be
Seq
LDrv
shutdown by pulling the soft-start pin below
0.3V. In shutdown by this method, the high side
driver is turned off, and the low side driver is
Rt
SS/ SD
Gnd
Sync Comp
PGnd
Vsns
Fb
R A
turned on. Thus, in this method, the output
voltage can be actively discharged through the
synchronous FET. Normal operation is
resumed by cycling the voltage at the Soft Start
Vin2
R B
pin.
Vo (Master)
Vcc
Vcc
Enable
Boot
HDrv
Vo (Salve)
PGood2
SW
Output Voltage Sequencing
The IR3640 can accommodate a full spectrum
of user programmable sequencing option
R E
R F
Seq>0.85V
(steady state)
PGood
Seq
Rt
SS/ SD
Gnd
OCSet
LDrv
PGnd
Vsns
Sync Comp
Fb
R C
using Seq, Enable and Power Good pins.
06/15/2009
R D
Note: Vo (Master) > Vo (Salve)
Fig. 9b: Application Circuit for
Simultaneous Sequencing
12
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