参数资料
型号: IR3876MTRPBF
厂商: International Rectifier
文件页数: 12/21页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 12A 17QFN
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 4,000
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.5 V ~ 12 V
输入电压: 3 V ~ 21 V
频率 - 开关: 可调至 1MHz
电流 - 输出: 12A
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-PowerVQFN
包装: 带卷 (TR)
供应商设备封装: PQFN(5x6)
IR3876MPBF
CIRCUIT DESCRIPTION
UNDER/OVER VOLTAGE MONITOR
The IR3876 monitors the voltage at the FB node
through a 350ns filter. If the FB voltage is below
the under voltage threshold, UV# is set to LOW
holding PGOOD to be LOW. If the FB voltage is
above the over voltage threshold, OV# is set to
LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD
signal is pulled low. Toggling VCC or EN will
allow the next start up. Figure 18 shows
OVER CURRENT MONITOR
The over-current circuitry monitors the output
current during each switching cycle. The
voltage across the lower MOSFET, VPHASE, is
monitored for over current and zero crossing.
The OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower
MOSFET is gated on. This delay functions to
filter out switching noise. The minimum lower
gate interval allows time to sample VPHASE.
PGOOD
status
change
when
UV/OV
is
detected. The over voltage and under voltage
thresholds can be found in the Electrical
Specification section.
The over current trip point is programmed with
a resistor from the ISET pin to PHASE pin, as
shown in equation 4, where Tj is the junction
temperature of Q2 at operation conditions, and
0.4 is the temperature coefficient (~4000
ppm/ ? C) of Q2 R DSON . When over current is
detected, the output gates are tri-state and SS
voltage is pulled to 0V. This initiates a new soft
start cycle. If there is a total of four OC events,
the IR3876 will disable switching, as shown in
Figure 19. Toggling VCC or EN will allow the
next start up.
R SET ?
R DSON ? I OC
20 ? A
? (1 ?
T j ? 25
100
? 0.4)
(4)
Figure 18(a). Under/Over Voltage Monitor
* typical filter delay
Figure 19. Over Current Protection
Figure 18(b). Over Voltage Protection
12
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