参数资料
型号: IR3876MTRPBF
厂商: International Rectifier
文件页数: 17/21页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 12A 17QFN
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 4,000
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.5 V ~ 12 V
输入电压: 3 V ~ 21 V
频率 - 开关: 可调至 1MHz
电流 - 输出: 12A
同步整流器:
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-PowerVQFN
包装: 带卷 (TR)
供应商设备封装: PQFN(5x6)
IR3876MPBF
LAYOUT RECOMMENDATION
Bypass Capacitor:
One 1μF high quality ceramic capacitor should be
placed as near VCC pin as possible. The other
end of capacitor can be connected to a via or
V IN
connected directly to GND plane. Use a GND
plane instead of a thin trace to the GND pin
Q1
ON
because a thin trace have too much impedance.
Boot Circuit:
IR3876
V OUT
C BOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
Q2
OFF
C OUT
C IN
upper MOSFET turns on.
Power Stage:
Figure 23 shows the current paths and their
directions for the on and off periods. The on time
path has low average DC current and high AC
current. Therefore, it is recommended to place the
Figure 23. Current Path of Power Stage
input
ceramic
capacitor,
upper,
and
lower
MOSFET in a tight loop as shown in Figure 23.
The purpose of the tight loop from the input
ceramic
capacitor
is
to suppress
the
high
frequency (10MHz range) switching noise and
reduce Electromagnetic Interference (EMI). If this
path has high inductance, the circuit will cause
voltage spikes and ringing, and increase the
switching loss. The off time path has low AC and
high average DC current. Therefore, it should be
laid out with a tight loop and wide trace at both
ends of the inductor. Lowering the loop resistance
reduces the power loss. The typical resistance
value of 1-ounce copper thickness is 0.5 mΩ per
square inch.
17
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