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参数资料
| 型号： | IR5001SPBF |
| 厂商： | International Rectifier |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR/MOSFET UNIV N-CH 8SOIC |
| 标准包装： | 95 |
| 应用： | -48V Dist 电源系统，AdvancedTCA ? 系统 |
| FET 型： | N 沟道 |
| 输出数： | 1 |
| 内部开关： | 无 |
| 延迟时间 - 开启： | 27µs |
| 延迟时间 - 关闭： | 130ns |
| 电源电压： | 36 V ~ 75 V |
| 电流 - 电源： | 500µA |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
IR5001S & (PbF)
ABSOLUTE MAXIMUM RATINGS
Vline Voltage
Vcc Voltage
Icc Current
INN, INP Voltage
FETch, FETst
FETst Sink Current
Junction Temperature
Storage Temperature Range
-5.0V to 100V (continuous)
-0.5V to 15VDC
5mA
-5.0V to 100V (continuous)
-0.5V to 5.5V
10mA
-40°C to 125°C
-65°C to 150°C
CAUTION:
1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress only rating and operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V line = 36V to 100V; Vcc is decoupled with 0.1uF to
Gnd, C L =10nF at Vout; INP is connected to Gnd. Typical values refer to T A =25°C. Minimum and maximum limits
apply to T A = 0°C to 85°C temperature range and are 100% production-tested at both temperature extremes. Low
duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETERS
SYMBOL
TEST CONDITION
Vline=25V
MIN TYP MAX UNITS
0.14 0.3 0.5
Bias Section
Vline Bias Current
Iline
Vline=36V
0.2
0.5
0.75
mA
Vline=100V, Note 1
1.2
1.7
2.2
VCC output voltage
Vcc(out)
Vline=25V 10.2 12.5 14.1
V
Vline=open, VINP=0; VINN= -
UVLO Section
UVLO ON Threshold Voltage
Vcc(ON)
0.3V
Vcc increased until Vout switches
from LO to HI, Note 2
8.0 9.6 10.7
V
Vline=open, VINP=0, VINN=-
UVLO OFF Threshold Voltage
Vcc(OFF)
0.3V, Vcc is decreased until
5.6 7.2 8.8
Vout switches from HI to LO
UVLO Hysteresis
1.6
2.3
2.8
V
Input Comparator Section
VINP=0V and VINN Ramping up,
Input Offset Voltage (VINP-
Vos
VOUT changes from HI to LO,
-7.9
-4.0
0
VINN)
Fig.3
mV
Input Hysteresis Voltage
Vhyst
VINP=0,VINN ramping down,
Figures 3 and 4
13
31
44
(INN) Input Bias Current
(INP) Input Bias Current
I(INN)
I(INP)
VINP=0V, VINN=36V
VINN=0V, VINP=36V
0.2
0.2
0.5
0.5
0.9
0.9
mA
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