参数资料
型号: IRDC3839
厂商: International Rectifier
文件页数: 13/35页
文件大小: 0K
描述: KIT EVAL REG 6A SUPIRBUCK DC/DC
标准包装: 1
系列: SupIRBuck™
主要目的: DC/DC,LDO 步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 6A
输入电压: 12V
稳压器拓扑结构: 降压
频率 - 开关: 600kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: IR3839
IR3839MPbF
Vref
This pin reflects the internal reference voltage
which is used by the error amplifier to set the
output voltage. In most operating conditions this
pin is only connected to an external bypass
capacitor and it is left floating. In tracking mode
this pin should be connected to an external
voltage greater than 1.5V and less than 7V. For
margining applications, an external voltage
source is connected to Vref pin and overrides
the internal reference voltage. The external
voltage source should have a low internal
resistance (<100 ? ) and be able to source and
sink more than 25μA.
Fig. 4a. Recommended startup for
Normal operation
Pvin (12V)
Vcc (5.2V)
Enable > 1. 2 V
SS
Vp
Pre-Bias Startup
IR3839 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET (sync FET)
off until the first gate signal for control MOSFET
(control FET) is generated. Figure 5a shows a
typical Pre-Bias condition at start up. The sync
FET always starts with a narrow pulse width
and gradually increases its duty cycle with a
step of 25%, 50%, 75% and 100% until it
reaches the steady state value. The number of
these startup pulses for the sync FET is
internally programmed. Figure 5b shows a
series of 32, 16, 8 startup pulses.
Fig. 4b. Recommended startup for sequencing
operation (ratiometric or simultaneous)
Fig. 5a. Pre-Bias startup
Fig. 4c. Recommended startup for memory
tracking operation (Vtt-DDR)
Rev 1.41
Fig. 5b. Pre-Bias startup pulses
13
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