参数资料
型号: IRDC3839
厂商: International Rectifier
文件页数: 20/35页
文件大小: 0K
描述: KIT EVAL REG 6A SUPIRBUCK DC/DC
标准包装: 1
系列: SupIRBuck™
主要目的: DC/DC,LDO 步降
输出及类型: 1,非隔离
输出电压: 1.8V
电流 - 输出: 6A
输入电压: 12V
稳压器拓扑结构: 降压
频率 - 开关: 600kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: IR3839
IR3839MPbF
Application Information
V o ? V ref ? ? ? 1 ? 8 ? ? .......... .......... .......... .....(8)
Design Example:
The following example is a typical application for
IR3839. The application circuit is shown on page
26.
V in = 12 V ( 13 . 2 V max)
? R ?
? R 9 ?
When an external resistor divider is connected to
the output as shown in figure 16.
Equation (8) can be rewritten as:
R 9 ? R 8 ? ?
? .......... .......... .......... .... (9)
?
V o = 1 . 8 V
I o = 6 A
Δ V o ≤ ? 2 % ? V o for 30 % load transient )
? V ref
?
? V o ? V ref
?
?
F s = 600 kHz
For the calculated values of R8
feedback compensation section.
and R9 see
Enabling the IR3839
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage as shown in figure
15.
IR3839
IR3624
Fb
V OU T
R 8
R 9
V in
IR3839
Enable
R 1
Fig. 16. Typical application of the IR3839 for
programming the output voltage
? V EN ? 1.2 .......... (6)
V in (min) *
R 2 ? R 1
V EN
R 2
Fig. 15. Using Enable pin for UVLO
implementation
For a typical Enable threshold of V EN = 1.2 V
R 2
R 1 ? R 2
.......... (7)
V in( min ) ? V EN
For a V in (min) =10.2V, R 1 =49.9K and R 2 =6.8k ohm
is a good choice.
Programming the frequency
For F s = 600 kHz, select R t = 23.7 k ? , using
Table 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.6V. The divider ratio
is set to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
Rev 1.41
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected to
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6). The operation
of the circuit is as follows: When the sync FET is
turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards V cc through the internal bootstrap diode
(figure 17), which has a forward voltage drop V D .
The voltage V c across the bootstrap capacitor
C6 is approximately given as
V c ? V cc ? V D .......... .......... ...... (10)
When the control FET turns on in the next cycle,
the capacitor node connected to SW rises to the
bus voltage V in . However, if the value of C6 is
appropriately chosen, the voltage V c across C6
remains approximately unchanged and the
voltage at the Boot pin becomes:
V Boot ? V in ? V cc ? V D .......... .......... .......... .......... (11)
20
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