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参数资料
| 型号： | IRDC3856W |
| 厂商： | International Rectifier |
| 文件页数： | 22/34页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL SUPIRBUCK IR3856W |
| 产品培训模块： | SupIRBuck? Family and POL Design Tools Overview |
| 标准包装： | 1 |
| 系列： | SupIRBuck™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 600kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | IR3856W |
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PD-97506
IR3856WMPbF
Z I N
V OUT
C 3
Compensator
Type
F ESR vs F o
Output
Capacitor
C 7
R 10
R 8
R 3
C 4
Z f
Type II
F LC <F ESR <F o <F s /2
Electrolytic
Tantalum
R 9
Fb
E/A
Comp
Ve
Type III
F LC <F o <F ESR
Tantalum
Ceramic
Gain(dB)
H(s) dB
V REF
The higher the crossover frequency, the
potentially faster the load transient response.
However, the crossover frequency should be low
enough to allow attenuation of switching noise.
Typically, the control loop bandwidth or crossover
F Z 1
F Z 2
F P 2
F P 3
Frequency
frequency is selected such that
F o ≤ ( 1/5 ~ 1/10 ) * F s
F P 2 =
.......... .......... .......... .......... .......(27 )
F P 3 =
?
.......... ..... (28)
2 π * R 3 ? ? 4
? C * C 3 ? 2 π * R 3 * C 3
?
Fig.15. Type III Compensation network and
its asymptotic gain plot
The compensation network has three poles and
two zeros and they are expressed as follows:
F P 1 = 0 .......... .......... .......... .......... .......... .......... ......(26)
1
2 π * R 10 * C 7
1 1
?
? C 4 + C 3 ?
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45 o for overall stability.
For this design we have:
V in =12V
V o =1.8V
V osc =1.8V
V ref =0.7V
L o =1 uH
C o =4x22uF, ESR=3mOhm each
It must be noted here that the value of the
capacitance used in the compensator design
.......... .......... .......... .......... .....(29)
?
.......... (30)
F Z 1 =
F Z 2 =
1
2 π * R 3 * C 4
1 1
2 π * C 7 * ( R 8 + R 10 ) 2 π * C 7 * R 8
must be the small signal value. For instance, the
small signal capacitance of the 22uF capacitor
used in this design is 12uF at 1.8 V DC bias and
600 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
Cross over frequency is expressed as:
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
V in 1
V osc 2 π * L o * C o
F o = R 3 * C 7 *
*
.......... .......... .......... .. (31)
stage transfer function of the converter and
measuring the double pole frequency F LC and
using equation (16) to compute the small signal
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of the
crossover frequency.
Rev 9.0
C o .
These result to:
F LC =22.97 kHz
F ESR =4.4 MHz
F s /2 =300 kHz
Select crossover frequency: F o =100 kHz
Since F LC <F o <F s /2<F ESR , TypeIII is selected to
place the pole and zeros.
22
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